MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1188

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.10.14 PCI Express Controller Core Clock Ratio Register—0x440
The PCI Express controller core clock ratio register, shown in
of the actual PCI Express controller clock frequency to the default controller core frequency (333 MHz).
This is required only when a PCI Express controller clock frequency other than the default 333 MHz has
to be used.
17-92
Status Code
(Hex)
1C
1D
1A
1B
1E
1F
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Configuration lane number wait (3)
Configuration lane number accept
Configuration complete (0)
Configuration complete (1)
Configuration idle (0)
Configuration idle (1)
L0
TX L0; RX L0s entry
TX L0; RX L0s idle
TX L0; RX L0s fast training sequence (FTS)
TX L0s entry (0); RX L0
TX L0s entry (0); RX L0s idle
TX L0s entry (0); RX L0s FTS
TX L0s entry (1); RX L0
TX L0s entry (1); RX L0s idle
TX L0s entry (1); RX L0s FTS
TX L0s idle; RX L0
TX L0s idle; RX L0s entry
TX L0s idle; RX L0s idle
TX L0s idle; RX L0s FTS
TX L0s FTS; RX L0
TX L0s FTS; RX L0s entry
TX L0s FTS; RX L0s idle
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
LTSSM State Description
Table 17-111. PEX_LTSSM_STAT Status Codes (continued)
Status Code
(Hex)
4C
37
38
39
3A
3F
7F
49
4A
4B
60
61
62
68
69
6A
6B
75
71
72
73
74
78
Figure
Recovery idle (0)
Recovery idle (1)
Recovery to configuration
Recovery cfg to configuration
L0 no training
Detect quiet EI
Configuration link width start—RC
Configuration link width accept—RC
Configuration lane number wait—RC
Configuration lane number accept—RC
Loopback slave active (0)
Loopback slave active (1)
Loopback slave exit
Hot reset (0)
Hot reset (1)
Hot reset (0)—RC
Hot reset (1)—RC
Disabled (0)
Disabled (1)
Disabled (2)
Disabled (3)
Disabled (4)
L0 to L1/L2—RC
17-115, is used to program the ratio
LTSSM State Description
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