MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1608

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
25.4.3
If MSRCID0 is low when sampled during POR, the LBC is selected as the source for the debug
information appearing on MSRCID[0:4] and MDVAL. For more information on this mode, see
Section 13.1.3.2, “Source ID Debug Mode.”
25.4.4
The watchpoint monitor (WM) can be programmed to arm and trigger on many different events including
any of the following:
A watchpoint event can be used in the following ways:
The large counters available in the performance monitor block and the interlock between it and the
watchpoint monitor support sophisticated debug scenarios.
A WM trigger event may be composed of several events programmed in the watchpoint monitor control
registers (WMCR0–WMCR1). Because the watchpoint monitor is disabled by default during POR, these
registers must be initialized to make use of this debug feature. Note that the WM address mask register
(WMAMR) and the type mask register (WMTMR) are cleared during POR. This means that the
watchpoint monitor’s default behavior following a power-on reset is to trigger on any address and no
transaction type. The reset value of WMCR0[TMD] is 0 which means transaction matching is enabled but
since no transaction is selected (WMTMR=0), a match will never occur. Either the transaction matching
must be disabled by setting WMCR0[TMD] to a value of 1, or valid transactions must be selected by
setting one or more of the WMTMR bits to a value of 1.
25.4.4.1
The WM can produce a performance monitor (PM) event with every trigger. This is accomplished by
configuring the performance monitor to count WM events. For more information on this configuration see
the events named ‘Number of watchpoint monitor hits’ and ‘Number of trace buffer hits’ in
Multi-level triggers can be created using the watchpoint monitor, the performance monitor, and the trace
buffer combined. For example, the WM can be programmed to trigger on events that also increment a PM
counter (the performance monitor must also be programmed to respond to this event), the output of which
(perfmon_overflow) could trigger the start of tracing in the trace buffer.
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External event (through TRIG_IN)
A trace buffer event
A performance monitor overflow event
A comparison of the current and programmed context ID registers
Trigger a logic analyzer (using TRIG_OUT)
Arm or trigger the trace buffer
Trigger a performance monitor event
Local Bus Interface Debug
Watchpoint Monitor
Watchpoint Monitor Performance Monitor Events
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor
Table
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