MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 938

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.6.5.3.1
PBQ is the simplest scheduler decision policy. The enabled TxBD rings are assigned a priority value based
on their index. Rings with a lower index have precedence over rings with higher indices, with priority
assessed on a frame-by-frame basis. For example, frames in TxBD ring 0 have higher priority than frames
in TxBD ring 1, and frames in TxBD ring 1 have higher priority than frames in TxBD ring 2, and so on.
The scheduling decision is then achieved as follows:
14.6.5.3.2
eTSEC implements a modified weighted round-robin scheduling algorithm across all enabled TxBD rings
when TCTRL[TXSCHED] = 10. In MWRR, the weights in the TR03WT and TR47WT registers
determine the ideal size of each transmit slot, as measured in multiples of 64 bytes. Thus, to set a transmit
slot of 512 bytes, a weight of 512/64 or 8 needs to be set for the ring. In this mode TxBD rings 1–7 are
selected in round-robin fashion, whereas TxBD ring 0, if enabled with ready data for transmission, is
always selected in between other rings so as to expedite transmission from ring 0.
The scheduling decision is then achieved as follows:
14-190
loop
endloop
for ring = 1..7 and enabled(ring) loop
endloop
for ring = 1..7 and enabled(ring) loop
# start or S/W clear of TSATn
ring = 0;
while ring <= 7 loop
endloop
credit[ring] = 0;
if not ring_empty(0) then
endif
if not ring_empty(ring) then
endif
while credit[ring] > 0 loop
if enabled(ring) and not ring_empty(ring) then
else
endif
credit[0] = credit[0] + weight[0];
while credit[0] > 0 loop
endloop
credit[ring] = credit[ring] + weight[ring];
transmit_frame(ring);
credit[ring] = credit[ring] - frame_size;
if ring_empty(ring) then
endif
Priority-Based Queuing (PBQ)
Modified Weighted Round-Robin Queuing (MWRR)
transmit_frame(ring);
ring = 0;
ring = ring + 1;
transmit_frame(0);
credit[0] = credit[0] - frame_size;
if ring_empty(0) then
endif
credit[ring] = 0;
credit[0] = 0;
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor