MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 336

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
The address and command interface is also source synchronous, although 1/8 cycle adjustments are
provided for adjusting the clock alignment.
Figure 8-46
Figure 8-47
Figure 8-48
nine 8M 8 DDR modules for a total of 256 Mbytes of system memory. One of the nine modules is used
for the memory’s ECC checking function. Certain address and control lines may require buffering.
Analysis of the device’s AC timing specifications, desired memory operating frequency, capacitive loads,
and board routing loads can assist the system designer in deciding signal buffering requirements. The DDR
memory controller drives 16 address pins, but in this example the DDR SDRAM devices use only 12 bits.
8-62
shows an example DDR SDRAM configuration with four logical banks.
shows some typical signal connections.
shows an example DDR SDRAM configuration with four physical banks each comprised of
MCS, MRAS, MCAS, MWE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 8-46. Typical Dual Data Rate SDRAM Internal Organization
BANK ADDR
CKE, MCK, MCK
COMMAND:
ADDR
MRAS
MCAS
‘SUB’
MWE
MCS
MCK
MCK
Figure 8-47. Typical DDR SDRAM Interface Signals
CKE
BA1,BA0
DM
ADDR
DQM
13
2
SDRAM
Control
A[12:0]
BA[1:0]
Write Enable
64M x 1 Byte
Command
Bus
CK
512 Mbit
Data-Out Registers
Logical
Bank 0
DQ[7:0]
DQS
Logical
Bank 1
Read Data Latch
MUX, MASK,
Data Bus
8
Logical
Bank 2
Data-In Registers
DATA
DATA
STROBE
Logical
Bank 3
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