MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 411

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 9-36
Note the following:
9.3.7.1
The EIVPRs, shown in
those caused by the assertion of any of IRQ[]. See
information on IPR and ISR.
Offset EIVPR0: 0x0000; EIVPR1: 0x0020; EIVPR2: 0x0040; EIVPR3: 0x0060; EIVPR4:
Reset
Table 9-38
Freescale Semiconductor
Bits
Message signaled
0
1
W
R
•
•
•
0x0080; EIVPR5: 0x00A0; EIVPR6: 0x00C0; EIVPR7: 0x00E0; EIVPR8: 0x0100;
EIVPR9: 0x0120; EIVPR10: 0x0140; EIVPR11: 0x0160
MSK
Global timer
Messaging
The MSK, A, PRIORITY, and VECTOR fields have meaning only for interrupts routed to the int
signal.
The polarity field, P, is provided to indicate whether the signals from the corresponding source are
active high or low.
The sense field, S, is provided to allow external interrupt sources to be configured as level-sensitive
so they can be routed to either cint or IRQ_OUT.
0
1
Interrupt Source
Name
MSK
External
A
Internal
A
0
describes the EIVPR fields.
1
shows the vector/priority registers.
External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11)
2
0 0 0 0
Figure 9-38. External Interrupt Vector/Priority Registers (EIVPR0
Mask. Mask interrupts from this source. MSK affects only interrupts routed to int .
0 An interrupt request is generated if the corresponding IPR bit is set.
1 Further interrupts from this source are disabled.
Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values should
not be changed while this bit is set. Affects only interrupts routed to int .
0 No current interrupt activity associated with this source.
1 The interrupt field for this source is set in the IPR or ISR.
(Section
(Section
(Section
(Section
(Section
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Figure
9.3.2.4)
9.3.6.4)
9.3.7.5)
9.3.7.3) R
9.3.7.1) R
0
0
7
Figure 9-37. Vector/Priority Register Summary
9-38, contain polarity and sense fields for the external interrupts, that is,
W
W
W
R
P S
0
8
Table 9-38. EIVPR n Field Descriptions
MSK
MSK
MSK
0
9
10 11 12
0
—
A
A
A
0
0
1
0
PRIORITY
—
—
0
Section 9.4.1, “Flow of Interrupt Control,”
0
6
—
15 16
0
P
P S
Description
7
0
8
0
—
9 10 11
—
0
PRIORITY
PRIORITY
PRIORITY
0
0
0
Programmable Interrupt Controller (PIC)
14 15
0
VECTOR
0
–
EIVPR11)
0
0
VECTOR
VECTOR
VECTOR
0
0
for
0
0
Access:
Mixed
0
9-41
31
0
31