MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 658

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
Enhanced Local Bus Controller
13.3.1.2.3
Figure 13-4
13-16
Offset OR0: 0x0_5004
Reset
Reset
Refer to
Bits
30
31
W
W
R
R
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
OR4: 0x0_5024
OR5: 0x0_502c
OR6: 0x0_5034
OR7: 0x0_503c
AM
16
0
Name
EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read
Table 13-5
EAD
shows the bit fields for ORn when the corresponding BRn[MSEL] selects the FCM machine.
17
Option Registers (OR n )—FCM Mode
access from the current bank and the next access.
External address latch delay. Allow extra bus clock cycles when using external address latch (LALE).
0 No additional bus clock cycles (LALE asserted for one bus clock cycle only)
1 Extra bus clock cycles are added (LALE is asserted for the number of bus clock cycles specified by
—
LCRR[EADC]).
for the OR0 reset value. All other option registers have all bits cleared.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
18
TRLX
BCTLD
Table 13-7. OR n
0
0
1
1
19
Figure 13-4. Option Registers (OR n ) in FCM Mode
20
—
EHTR
0
1
0
1
PGS CSCT CST
21
—
The memory controller generates normal timing. No additional
cycles are inserted.
1 idle clock cycle is inserted.
4 idle clock cycles are inserted.
8 idle clock cycles are inserted.
GPCM Field Descriptions (continued)
22
23
All zeros
All zeros
AM
Description
CHT
24
1
25
SCY
Meaning
27
RST
28
Freescale Semiconductor
TRLX
29
Access: Read/Write
EHTR
30
—
15
31