MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 656

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
Enhanced Local Bus Controller
13.3.1.2.2
Figure 13-3
Table 13-7
13-14
Offset OR0: 0x0_5004
Reset
Reset
17–18
0–16
Refer to
Bits
19
20
W
W
R
R
OR1: 0x0_500c
OR2: 0x0_5014
OR3: 0x0_501c
OR4: 0x0_5024
OR5: 0x0_502c
OR6: 0x0_5034
OR7: 0x0_503c
AM
16
0
BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank.
Name
CSNT Chip select negation time. Determines when LCS n and LWE are negated during an external memory write
Table 13-5
AM
—
describes ORn fields for GPCM mode.
shows the bit fields for ORn when the corresponding BRn[MSEL] selects the GPCM machine.
17
Option Registers (OR n )—GPCM Mode
GPCM address mask. Masks corresponding BR n bits. Masking address bits independently allows external
devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map.
0 Corresponding address bits are masked and therefore don’t care for address checking.
1 Corresponding address bits are used in the comparison between base and transaction addresses.
Reserved
0 LBCTL is asserted upon access to the current memory bank.
1 LBCTL is not asserted upon access to the current memory bank.
access handled by the GPCM, provided that ACS
of CSNT). This helps meet address/data hold times for slow memories and peripherals.
0 LCS n and LWE are negated normally.
1 LCS n and LWE are negated one quarter of a bus clock cycle earlier.
—
Table 13-6. Memory Bank Sizes in Relation to Address Mask (continued)
for the OR0 reset value. All other option registers have all bits cleared.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
18
BCTLD CSNT
19
1111_1111_1111_1111_0
1111_1111_1111_1111_1
Figure 13-3. Option Registers (OR n ) in GPCM Mode
Table 13-7. OR n
20
AM
21
ACS
22
—
XACS
GPCM Field Descriptions
23
All zeros
All zeros
AM
Description
24
00 (when ACS = 00, only LWE is affected by the setting
1
Memory Bank Size
SCY
64 Kbytes
32 Kbytes
27
SETA
28
Freescale Semiconductor
TRLX
29
Access: Read/Write
EHTR
30
EAD
15
31