MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 180

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
More information on system booting is given later in this chapter. See
Figure 4-5
4-10
HRESET_REQ
1
POR Configs
PLL Configs
Multiplexed with TRIG_OUT.
11. When the local bus FCM and boot sequencer complete, the PCI Express interfaces begin training,
12. The ASLEEP signal negates synchronized to a rising edge of SYSCLK, indicating the ready state.
HRESET
SRESET
SYSCLK
TRESET
ASLEEP
READY
the PCI and PCI Express interfaces are released to accept external requests, and the boot vector
fetched by the e500 core is allowed to proceed unless processor booting is further held off by POR
configuration inputs as described in
is now in its ready state.
The ready state is also indicated by the assertion of READY/TRIG_OUT if TOSR[SEL] = 000. In
this case, READY is asserted with the same rising edge of SYSCLK, to indicate that the device has
reached its ready state. See
information on this register.
Asserting READY allows external system monitors to know basic device status, for example,
exactly when it emerges from reset, or if the device is in a low-power mode. For more information
on the debug functions of TRIG_OUT, see
information about power management states, see
shows a timing diagram of the POR sequence.
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(high impedance)
(High Impedance)
(High Impedance)
Figure 4-5. Power-On Reset Sequence
Section 25.3.4.1, “Trigger Out Source Register (TOSR),”
Section 4.4.3.10, “CPU Boot Configuration.”
Section 25.3.4, “Trigger Out Function.”
Section 23.4.1, “Register Descriptions.”
Section 4.5.1, “System
Freescale Semiconductor
The MPC8536E
For more
for more
Boot.”