MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1211

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4.4
All device power states are supported with the exception of D3cold with Vaux. In addition, all link power
states are supported with the exception of L2 states. Only L0s ASPM mode is supported if enabled by
configuring the Link Control register’s bits 1–0 in configuration space. Note that there is no power saving
in the controller when the device is put into a non-D0 state. The only power saving is the I/O drivers when
the controller is put into a non-L0 link state.
17.4.4.1
The L2/L3 Ready link state is entered after the EP device is put into a D3hot state followed by a
PME_Turn_Off/PME_TO_Ack message handshake protocol. Exiting this state requires a POR reset or a
WAKE signal from the EP device. The PCI Express controller (in EP mode) does not support the
generation of beacon; therefore, as an alternative, the device can use one of the GPIO signals as an enable
to an external tristate buffer to generate a WAKE signal, as shown in
Freescale Semiconductor
Component
D-State
D3cold
D3hot
D0
D1
D2
Power Management
L2/L3 Ready Link State
L0, L0s, L1, L2/L3
Interconnect
Permissible
L0, L0s, L1
L0, L0s, L1
CPLD (Memory Read Completion, IO Read
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
L0, L0s
CPLH (Memory Read Completion, IO R/W
Ready
State
L3
Completion, Cfg Read Completion)
Completion, Cfg R/W Completion)
Table 17-128. Power Management State Supported
In full operation.
All outbound traffics are stalled. All inbound traffic is thrown away. The only exceptions
are PME messages and configuration transactions. If the device is in RC mode, it is
permissible to send a PM_Turn_Off message through the PEX Power Management
Command register.
All outbound traffics are stalled. All inbound traffic is thrown away. The only exceptions
are PME messages and configuration transactions. If the device is in RC mode, it is
permissible to send a PM_Turn_Off message through the PEX Power Management
Command register.
All outbound traffics are stalled. All inbound traffic is thrown away. The only exceptions
are PME messages and configuration transactions. If the device is in RC mode, it is
permissible to send a PM_Turn_Off message through the PEX Power Management
Command register. Note that if a transition of D3hot->D0 occurs, a reset is performed
to the controller’s configuration space. In addition, link training restarts.
Completely off.
Credit Type
Table 17-127. Initial credit advertisement
Initial Credit Advertisement
Action
Figure
Infinite
Infinite
17-132.
PCI Express Interface Controller
17-115