MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 402

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.3.3.6
Figure 9-23
Table 9-25
9.3.3.7
Figure 9-24
Table 9-26
9.3.4
The twelve performance monitor mask registers consist of four sets of three 32-bit registers, PMnMR0,
PMnMR1, and PMnMR2. Each set can be configured to select one interrupt source (interprocessor, timer,
message, shared message signaled, external, or internal) to generate a performance monitor event. The
performance monitor can be configured to track this event in the performance monitor local control
registers. See
9-32
0–31 INT n Internal interrupts 0–31. Bit 0 represents INT0. Bit 31 represents INT31.
0–31
Bits Name
Bits
Offset 0x1344
Reset
Offset 0x1340
Reset
W
W
R
R
Name
INT n Internal interrupts 32–63. Bit 0 represents INT32. Bit 31 represents INT63.
0
0
describes CISR1.
describes CISR2.
Performance Monitor Mask Registers (PMMRs)
shows the CISR1.
shows the CISR2.
0 Corresponding interrupt is not active or not routed to cint .
1 The corresponding interrupt is active and is routed to the cint (if the corresponding x IDR n [CI] is set).
0 Corresponding interrupt is not active or not routed to cint .
1 The corresponding interrupt is active and is routed to the cint , if the corresponding x IDR n [CI] is set.
Critical Interrupt Summary Register 1 (CISR1)
Critical Interrupt Summary Register 2 (CISR2)
Section 24.3.2.2, “Performance Monitor Local Control Registers (PMLCAn, PMLCBn).”
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 9-23. Critical Interrupt Summary Register 1 (CISR1)
Figure 9-24. Critical Interrupt Summary Register 2 (CISR2)
Table 9-25. CISR1 Field Descriptions
Table 9-26. CISR2 Field Descriptions
All zeros
All zeros
Description
15 16
Description
INT n
INT n
Freescale Semiconductor
Access: Read only
Access: Read only
31
31