MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1144

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
PCI Express Interface Controller
.
17.3.8.1.5
The revision ID register, shown in
.
17-48
The definition of each bit is given in
Table 17-41
10–9
Offset 0x08
Reset
Bits
The error control and status bits in the command and status registers control PCI-compatible error reporting. PCI Express
advanced error reporting is controlled by the PCI Express device control register described in
Device Control
17.3.10.12.
7–5
2–0
15
14
13
12
11
8
4
3
W
R
Signaled system error
Received target-abort
Signaled target-abort
Detected parity error
Master data parity
Bits
7–0
Capabilities List
Interrupt Status
error detected
master-abort
7
describes the revision ID register fields.
Received
Register—0x54,” and the advance error reporting capability structure described in sections 17.3.10.1 through
Name
PCI Express Revision ID Register—Offset 0x08
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-41. PCI Express Revision ID Register Field Descriptions
1
Revision ID
1
Table 17-40. PCI Express Status Register Field Descriptions
Name
1
1
1
1
Set whenever a device receives a poisoned TLP regardless of the state of bit 6 in the command
register.
Set whenever a device sends a ERR_FATAL or ERR_NONFATAL message and the SERR
enable bit in the command register is set.
Set whenever a requestor receives a completion with unsupported request completion status.
Set whenever a device receives a completion with completer abort completion status.
Set whenever a device completes a request using completer abort completion status.
Reserved
Set by the requestor (primary side for Type1 headers) when either the requestor receives a
completion marked poisoned or the requestor poisons a write request. Note that the parity error
enable bit (bit 6) in the command register must be set for this bit to be set.
Reserved
All PCI Express devices are required to implement the PCI Express capability structure.
Set when an INTx interrupt message is pending internally to the device.
Note that this bit is associated with INTx messages and not Message Signaled Interrupts.
Reserved
Figure 17-41. PCI Express Revision ID Register
Figure
Table
Revision specific.
17-41, is used to identify the revision of the device.
17-40.
Revision specific
Revision ID
Description
Description
Section 17.3.9.8, “PCI Express
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