MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1078

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
Figure 16-51
Figure 16-52
16.4.2.8
A PCI transaction may be terminated by either the initiator or the target. The initiator is ultimately
responsible for concluding all transactions, regardless of the cause of the termination. All transactions are
concluded when PCI_FRAME and PCI_IRDY are both negated, indicating the bus is idle.
16.4.2.8.1
Normally, a master initiates termination by negating PCI_FRAME and asserting PCI_IRDY. This
indicates to the target that the final data phase is in progress. The final data transfer occurs when both
PCI_TRDY and PCI_IRDY are asserted. The transaction is considered complete when data is transferred
16-52
PCI_DEVSEL
PCI_FRAME
PCI_FRAME
PCI_EVSEL
PCI_TRDY
PCI_TRDY
PCI_C/BE
PCI_IRDY
PCI_C/BE
PCI_IRDY
Transaction Termination
illustrates a PCI single-beat write transaction.
illustrates a PCI burst write transaction.
SYSCLK
SYSCLK
PCI_AD
PCI_AD
Master-Initiated Termination
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 16-51. PCI Single-Beat Write Transaction
ADDR
ADDR
CMD
CMD
Figure 16-52. PCI Burst Write Transaction
Byte Enables 1 Byte Enables 2
DATA1
DATA2
Byte Enables
DATA
Byte Enables 3
DATA3
DATA4
BEs 4
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