MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 583

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x3_C038
10.7.7.8
The PKEU interrupt mask register (shown in
given error (as defined in
this register is set, then the error is disabled; no error interrupt occurs and the interrupt status register is not
updated to reflect the error. If the corresponding bit is not set, then upon detection of an error, the PKEU
interrupt status register is updated to reflect the error, causing assertion of the error interrupt signal, and
causing the module to halt processing.
Freescale Semiconductor
Table 10-71
W
R
58-63
0-48
Bits
Bits
0
57
49
50
51
52
53
describes the PKEU interrupt mask register fields.
PKEU Interrupt Mask Register
Table 10-70. PKEU Interrupt Status Register Field Descriptions (continued)
Name
Name
EVM
INV
AE
BE
CE
—
—
IE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-71. PKEU Interrupt Mask Register Field Descriptions
Section 10.7.7.7, “PKEU Interrupt Status
Address error. Illegal read or write address was detected within the PKEU address
space.
0 No error detected
1 Address error
Reserved
Reserved
Even modulus error
0 Even modulus error enabled
1 Even modulus error disabled
Inversion error
0 Inversion error enabled
1 Inversion error disabled
Internal error
0 Internal error enabled
1 Internal error disabled
Boot error
0 Boot error enabled
1 Boot error disabled
Context error
0 Context error enabled
1 Context error disabled
Figure 10-101. PKEU Interrupt Mask Register
ID
Figure
10-101) controls the result of detected errors. For a
48
Description
Description
EVM INV EI BE CE KSE DSE ME AE
49
50
Register”), if the corresponding bit in
51 52
53
54
Security Engine (SEC) 3.0
55
Access: Read/Write
56
57 58
10-153
—
63