MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1016

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA Controller
15.4.1.4
The channel continue mode (enabled when MRn[CC] is set) offers software the flexibility of having the
DMA controller get started on descriptors that have already been programmed while software continues
to build more descriptors in memory. Software can set the end-of-links descriptor (EOLND) in basic mode,
or end-of-lists descriptor (EOLSD) in extended mode, to cause the channel to go into a halted state while
software continues to build other descriptors in memory. Software can then set CC to force hardware to
continue where it left off. Channel continue is only meaningful for chaining modes, not direct mode.
If CC is set by software while the channel is busy with a transfer, the DMA controller finishes all transfers
until it reaches the EOLND in basic mode or EOLSD in extended mode. The DMA controller then
refetches the last link descriptor in basic mode, or the last list descriptor in extended mode and clears the
channel continue bit. If EOLND or EOLSD is still set for their respective modes, the DMA controller
remains in the idle state. If EOLND or EOLSD is not set, the DMA controller continues the transfer by
refetching the new descriptor. The channel busy (SRn[CB]) bit is cleared when the DMA controller
reaches EOLND/EOLSD and is set again when it initiates the refetch of the link or list descriptor.
If CC is set by software while the channel is not busy with a transfer, the DMA controller refetches the last
link descriptor in basic mode, or the last list descriptor in extended mode and clears the channel continue
bit. If EOLND or EOLSD is still set for their respective modes, the DMA controller remains in the idle
state. If the EOLND or EOLSD bits are not set, the DMA controller continues the transfer by refetching
the new descriptor.
15.4.1.4.1
On a channel continue, the descriptor at the current link descriptor address registers (CLNDARn and
ECLNDARn) is refetched to get the next link descriptor address field as updated by software. The channel
halts if NLNDARn[EOLND] is still set. If EOLND is zero, the next link descriptor address is copied into
CLNDARn and ECLNDARn and the channel continues with another descriptor fetch of the current link
descriptor address. As a result, two link descriptor fetches always exist after channel continue before
starting the first transfer.
15-30
DDONE
DREQ
DACK
EMP_EN
CLOCK
Transfer Start
Transfer In Progress
Basic Mode
Channel Continue Mode for Cascading Transfer Chains
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Transfer Done
Figure 15-23. External Control Interface Timing
Transfer Start
Transfer Pause
Freescale Semiconductor
Transfer Restart