MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1677

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Glossary
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this reference
manual.
A
B
Freescale Semiconductor
Autobaud. The process of determining a serial data rate by timing the width of a single bit.
Breakpoint. A programmable event that forces the core to take a breakpoint exception.
Architecture. A detailed specification of requirements for a processor or computer
Atomic access. A bus access that attempts to be part of a read-write operation to the same
Beat. A single state on the bus interface that may extend across multiple bus cycles. A
Big-endian. A byte-ordering method in memory where the address n of a word
Boundedly undefined. A characteristic of certain operation results that are not rigidly
Burst. A multiple-beat data transfer whose total size is typically equal to a cache block.
Bus clock. Clock that causes the bus state transitions.
MPC83536E PowerQUICC™ III Integrated Processor Reference Manual, Rev. 1
system. It does not specify details of how the processor or computer system must
be implemented; instead it provides a template for a family of compatible
implementations.
address uninterrupted by any other access to that address (the term refers to the
fact that the transactions are indivisible). The Power Architecture technology
implements atomic accesses through the lwarx/stwcx. instruction pair.
transaction can be composed of multiple address or data beats.
corresponds to the most-significant byte. In an addressed memory word, the bytes
are ordered (left to right) 0, 1, 2, 3, with 0 being the most-significant byte. See
Little-endian.
prescribed by the Power Architecture technology. Boundedly-undefined results
for a given operation may vary among implementations and between execution
attempts in the same implementation.
Although the architecture does not prescribe the exact behavior for when results
are allowed to be boundedly undefined, the results of executing instructions in
contexts where results are allowed to be boundedly undefined are constrained to
ones that could have been achieved by executing an arbitrary sequence of defined
instructions, in valid form, starting in the state the machine was in before
attempting to execute the given instruction.
Glossary-1