MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 920

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.6.3.10.1 Interrupt Coalescing
Interrupt coalescing offers the user the ability to contour the behavior of the eTSEC with regard to frame
interrupts. Separate but identical mechanisms exist for both transmitted frames and received frames. In
either case, frame interrupts require that software set the I-bit in RxBDs or TxBDs, and disable buffer
interrupts (IEVENT[RXB] or IEVENT[TXB]). Particular rings can remain free of interrupts by ensuring
that the I-bit is consistently cleared in all BDs. While interrupt coalescing is enabled, a transmit or receive
frame interrupt is raised either when a counter threshold-defined number of frames is received/transmitted
or the timer threshold-defined period of time has elapsed, whichever occurs first. Disabling and then
re-enabling interrupt coalescing forces reset of the coalescing timers and counters to reflect changes made
to the threshold registers.
14.6.3.10.2 Interrupt Coalescing By Frame Count Threshold
To avoid interrupt bandwidth congestion due to frequent, consecutive interrupts, the user may enable and
configure interrupt coalescing to deliberately group frame interrupts, reducing the total number of
14-172
Interrupt
Interrupt
GRSC
GTSC
RXC
RXB
TXC
RXF
TXB
TXF
•
•
Clear any set halt or frame interrupt bits in TSTAT and RSTAT registers, or DMACTRL[GTS] and
DMACTRL[GRS] by writing 1s to these bits.
Continue normal execution.
Graceful transmit stop complete: transmitter is put into a pause state
after completion of the frame currently being transmitted.
Transmit control: Instead of the next transmit frame, a control frame
was sent.
Transmit buffer: A transmit buffer descriptor, that is not the last one in
the frame, was updated in one of the enabled TxBD rings.
Transmit frame: A frame from an enabled TxBD ring was transmitted
and the last transmit buffer descriptor (TxBD) of that frame was
updated.
Graceful receive stop complete: Receiver is put into a pause state after
completion of the frame currently being received.
Receive control: A control frame was received. As soon as the
transmitter finishes sending the current frame, a pause operation is
performed.
Receive buffer: A receive buffer descriptor, that is not the last one of
the frame, was updated in one of the enabled RxBD rings.
Receive frame: A frame was received to an enabled RxBD ring and the
last receive buffer descriptor (RxBD) of that frame was updated.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-153. Non-Error Transmit Interrupts
Table 14-154. Non-Error Receive Interrupts
Description
Description
Programmable ‘write with response’ TxBD
to memory before setting IEVENT[TXB].
Programmable ‘write with response’ to
memory on the last TxBD before setting
IEVENT[TXF].
Programmable ‘write with response’ RxBD
to memory before setting IEVENT[RXB].
Programmable ‘write with response’ to
memory on the last RxBD before setting
IEVENT[RXF].
Action Taken by the eTSEC
Action Taken by the eTSEC
Freescale Semiconductor
None
None
None
None