MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 752

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14-4
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— VLAN insertion and deletion
— Retransmission following a collision
— Support for CRC generation and verification of inbound/outbound packets
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
MAC address recognition:
— Exact match on primary and virtual 48-bit unicast addresses
— Broadcast address (accept/reject)
— Hash table match on up to 256 unicast/multicast or 512 multicast-only addresses
— Promiscuous mode
Remote network monitoring (RMON) statistics support
— 32-bit byte counters
— Carry/Overflow of counter interrupts
Backward compatibility with MPC8540E/MPC8560E (PowerQUICC III) TSEC
— PowerQUICC III buffer descriptor (BD) format and rings supported
— Common register memory map, with specific exceptions:
— Reset state of eTSEC defaults to common PowerQUICC III TSEC subset
— TSEC_ID register permits TSEC versus enhanced TSEC differentiation
Hardware assist for 1588 compliant timestamping (1588 not supported in conjunction with SGMII
10/100)
— Per packet timestamp tag for Receive
— Programmable timestamp capture for Transmit
— Recognition of PTP packet
— Periodic Pulse Generation
— Self-correcting precision timer with nano-second resolution
— Phase aligned adjustable (divide by N) clock output
— Two 64-bit alarm (future time) registers for future time comparison
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
– Programmable VLAN tag to support metropolitan bridging
– VRRP and HSRP support for seamless router fail-over
– In addition to primary station address, up to fifteen additional exact-match MAC addresses
– Out-of-sequence transmit BD not supported
– Internal DMA BD pointers and data counts not visible
– MINFLR register not supported
supported
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor