MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1106

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.2
17.3.2.1
The PCI Express configuration address register, shown in
accesses to PCI Express internal and external configuration registers.
The fields of the PCI Express configuration address register are described in
Both root complex (RC) and endpoint (EP) configuration headers contain 4096 bytes of address space. To
access a register within the header, both the extended register number and the register number fields are
concatenated to form the 4-byte aligned address of the register. That is, the register address is extended
register number || register number || 0b00.
17.3.2.2
The PCI Express configuration data register, show in
configuration access. Note that accesses of 1, 2, or 4 bytes to the PCI Express configuration data register
17-10
16–20
21–23
24–29
30–31
8–15
Bits
1–3
4–7
Offset 0x000
Reset
0
W
R
EN
EXTREGN
0
FUNCN
REGN
Name
BUSN
DEVN
PCI Express Configuration Access Registers
EN
—
—
Figure 17-2. PCI Express Configuration Address Register (PEX_CONFIG_ADDR)
1
PCI Express Configuration Address Register (PEX_CONFIG_ADDR)
PCI Express Configuration Data Register (PEX_CONFIG_DATA)
—
3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Enable. This bit allows a PCI Express configuration access when PEX_CONFIG_DATA is accessed. If
this bit is cleared, writing to PEX_CONFIG_DATA has no effect and reading PEX_CONFIG_DATA
returns unknown data.
Reserved
is, the registers in the offset range from 0x100 to 0xFFF).
Function number. Function to access within specified device
Reserved
Extended register number. This field allows access to extended PCI Express configuration space (that
Bus number. PCI bus number to access
Device number. Device number to access on specified bus
Register number. 32-bit register to access within specified device
4
EXTREGN
Table 17-4. PEX_CONFIG_ADDR Field Descriptions
7
8
BUSN
Figure
All zeros
15 16
Description
Figure
17-3, is a 32-bit port for internal and external
DEVN
17-2, contains address information for
20 21
FUNCN
Table
23 24
17-4.
Freescale Semiconductor
REGN
Access: Read/Write
29 30 31
—