MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 557

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.5.8
Following a done interrupt, the read-only KEU data out register holds the f9 message authentication code.
A 64-bit value is returned. This value may be truncated to 32 bits for some applications. Writing to this
location results in an address error reflected in the KEU interrupt status register.
10.7.5.9
The KEU end of message register, shown in
message block has been written to the input FIFO (in channel-driven access, this signaling is done
automatically). The KEU will not process the last block of data in its input FIFO until this register is
written. Once the end of message register is written, the KEU processes any remaining data in the input
FIFO and generates the done interrupt.
The value written to this register does not matter. A read of this register always returns a zero value.
Freescale Semiconductor
Bits
62
63
Reset
Reset
Field
Field
Addr
Addr
R/W
R/W
Name
OFU
0
0
—
KEU Data Out Register (f9 MAC) (KEUDOR)
KEU End of Message Register (KEUEMR)
According to the ETSI/SAGE 3GPP specification for f9 (version 1.2), only
32 bits of the final MAC are used. This corresponds to the lower 4 bytes of
the KEU data out register.
Table 10-57. KEU Interrupt Mask Register Fields Description (continued)
Output FIFO underflow. The KEU output FIFO was read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 10-71. KEU Data Out Register (f9 MAC)
Figure 10-72. KEU End of Message Register
KEU Data Out Register (f9 MAC)
Figure
0x0000_0000_0000_0000
NOTE
KEU 0x3_E048
KEU 0x3_E050
10-72, is used to signal to the KEU that the final
R/W
—
R
0
Description
Security Engine (SEC) 3.0
63
63
10-127