MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 174

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.3.1
Table 4-4
4.3.1.1
The configuration, control, and status registers are memory mapped. The set of configuration, control, and
status registers occupies a 1-Mbyte region of memory. Their location is programmable using the CCSR
base address register (CCSRBAR). The default base address for the configuration, control, and status
registers is 0xFF70_0000 (CCSRBAR = 0x000F_F700). CCSRBAR itself is part of the local access block
of CCSR memory, which begins at offset 0x0 from CCSRBAR. Because CCSRBAR is at offset 0x0 from
the beginning of the local access registers, CCSRBAR always points to itself. The contents of CCSRBAR
are broadcast internally in the MPC8536E to all functional units that need to be able to identify or create
configuration transactions.
4.3.1.1.1
Updates to CCSRBAR that relocate the entire 1-Mbyte region of configuration, control, and status
registers require special treatment. The effect of the update must be guaranteed to be visible by the
mapping logic before an access to the new location is seen. To make sure this happens, these guidelines
should be followed:
4-4
Local Memory
Offset (Hex)
0x0_0000
0x0_0008
0x0_0010
0x0_0020
•
•
CCSRBAR should be updated during initial configuration of the device when only one host or
controller has access to the device.
When the e500 core is writing to CCSRBAR, it should use the following sequence:
shows the memory map for local configuration control registers.
– If the boot sequencer is being used to initialize, it is recommended that the boot sequencer
– If an external host on PCI is configuring the device, it should set CCSRBAR to the desired
– If the e500 core is initializing the device, it should set CCSRBAR to the desired final
– Read the current value of CCSRBAR using a load word instruction followed by an isync.
– Write the new value to CCSRBAR.
Local Configuration Control
Accessing Configuration, Control, and Status Registers
set CCSRBAR to its desired final location.
final location before the e500 core is released to boot.
location before enabling other I/O devices to access the device.
This forces all accesses to configuration space to complete.
Updating CCSRBAR
CCSRBAR—Configuration, control, and status registers base
address register
ALTCBAR—Alternate configuration base address register
ALTCAR—Alternate configuration attribute register
BPTR—Boot page translation register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 4-4. Local Configuration Control Register Map
Register
Access
R/W
R/W
R/W
R/W
0x000F_F700
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Freescale Semiconductor
Section/Page
4.3.1.1.2/4-5
4.3.1.2.1/4-6
4.3.1.2.1/4-6
4.3.1.3.1/4-7