MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 560

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.5.14 KEU Key Data Registers_1 and _2 (Confidentiality Key) (KEUKD n )
The first two KEU key data registers, shown in
key that is used for f8 encryption/decryption. The KEU key data register_1, (CK-high), holds the first 8
bytes (1–8). The KEU key data register_2, (CK-low), holds the second 8 bytes (9–16). The KEU key data
registers must be written before message processing begins and cannot be written while the block is
processing data, or else, a context error occurs. Reading from either of these registers causes an address
error, which is reflected in the KEU interrupt status register.
10.7.5.15 KEU Key Data Registers _3 and _4 (Integrity Key) (KEUKD n )
The third and fourth KEU key data registers, shown in
128-bit key that is used for f9 message authentication. The KEU key data register_3, (IK-high), holds the
first 8 bytes (1–8). The KEU key data register_4, (IK-low), holds the second 8 bytes (9–16). The KEU key
data registers must be written before message processing begins and cannot be written while the block is
processing data, or else, a context error occurs.
If f9 only mode is set in the KEU mode register, the integrity key data may be optionally written to the
KEU key data registers_1 and KEU key data registers_2. This eliminates the need for the host to offset
10-130
Address KEU 0x3_E408
Address KEU 0x3_E400
Reset
Reset
W
W
R
R
0
0
For descriptor operation, if the entire context is unloaded for later reuse, the
context data size must be 72 bytes, and the output consists of KEU IV_1,
KEU ICV_In, KEU IV_2, and six KEU context data registers. For
operations performing processing of partial messages, if the context is
unloaded, the PE bit in the KEU mode register must not be set. Also, for
partial message processing, if the context is reloaded, the INT bit in the
KEU mode register must not be set.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 10-75. KEU Key Data Register_1 (CK-high)
Figure 10-76. KEU Key Data Register_1 (CK-high)
Figure 10-77. KEU Key Data Register_2 (CK-Low)
Figure 10-78. KEU Key Data Register_2 (CK-Low)
KEU Key Data Register _1 (CK-high)
KEU Key Data Register _2 (CK-low)
Figure 10-76
NOTE
All zeros
All zeros
Figure 10-80
and
Figure
and
10-78, together hold one 128-bit
Figure
10-82, together hold one
Freescale Semiconductor
Access: Write-only
Access: Write-only
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