MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1049

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.1.4
When a PCI error is detected, the appropriate error bit is set in the PCI error detect register. Subsequent
errors set the appropriate error bits in the error detection registers, but relevant information (attributes,
address, and data) is captured only for the first error. The PCI error detect register is a write-1-to-clear type
register. That is, reading from this register occurs normally; however, write operations are different in that
the bits can be cleared but not set. A bit is cleared whenever the register is written, and the data in the
corresponding bit location is a 1. For example, to clear bit 25 and not affect any other bits in the register,
the value 0x0000_0040 is written to the register.
The error bit is set regardless of the state of the corresponding error enable bit in the PCI error enable
register. The error enable bits are used to send or block the error reporting to the interrupt mechanism. The
interrupt can be cleared by writing 0xFFFF_FFFF to the PCI error detect register.
A master-abort condition during a configuration cycle is not necessarily an error. In this case, if relevant,
the master abort error enable can be disabled to prevent the reporting of master-aborts during outbound
configuration cycles. Master-aborts during configuration reads return 0xFFFF_FFFF.
For an inbound configuration write transaction with a parity error, the device always updates the register
access and generates the error interrupt if the interrupt enabled bit is set.
See
Freescale Semiconductor
20–25
26–31 IWS Inbound window size. Inbound translation window size N which is the encoded 2^(N+1) bytes window
Section 16.4.2.13, “PCI Error Functions,”
Bits Name
—
PCI Error Management Registers
Reserved
size. The smallest window is 4 Kbytes.
000000 Reserved
...
001011 4-Kbyte window size
001100 8-Kbyte window size
...
011111 4-Gbyte window size
100000 8-Gbyte window size
100001 16-Gbyte window size
100010 Reserved
...
111111 Reserved
For configuration and run-time registers, the window size is fixed at
010011 1-Mbyte window size
For register set 0, the window size is limited to 4 Gbytes or smaller.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 16-14. PIWAR n Field Descriptions (continued)
for more detail on error handling.
Description
PCI Bus Interface
16-23