MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1246

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
19.3.3.2
SError, shown in
to complement the error information available in the shadow register block error register. The register
represents all the detected errors accumulated since the last time the SError register was cleared (whether
recovered by the interface or not). Set bits in the error register are explicitly cleared by a write operation
to the SError register or by a reset operation. The error bits that have been set in this register are cleared
by writing a 1 to the corresponding field. Host software should clear the interface SError register at
appropriate checkpoints in order to best isolate error conditions and the commands they impact.
Bits 31–16 of this register represent the DIAG decode bits, which contain diagnostic error information, for
use by diagnostic software in validating correct operation or isolating failure modes. Bits 15–0 represent
the ERR decode bits, which contain information for use by the host software in determining the appropriate
response to the error condition.
Table 19-14
19-16
31–28
Bit
Offset 0x1_8104
Reset
W
R
7–4
3–0
Bit
31
—
Name
describes the SError field descriptions.
SATA Interface Error Register (SError)
28
—
Name
SPD
DET
w1c w1c w1c
27
A
Figure
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
26
Reserved bit for future use. Should be cleared.
X
Speed. Indicates the negotiated interface communication speed established.
0000 No negotiated speed (device not present or communication not established)
0001 First-generation communication rate negotiated
0010 Second-generation communication rate negotiated
All other values reserved
Detection. Indicates the interface device detection and PHY state.
0000 No device detected and PHY communication not established
0001 Device presence detected but PHY communication not established
0011 Device presence detected and PHY communication established
0100 PHY in offline mode as a result of the interface being disabled or running in a BIST
All other values reserved
19-14, is a 32-bit register that conveys supplemental interface error information
25
F
Figure 19-14. SATA Interface Error Register (SError)
Table 19-13. SStatus Field Descriptions (continued)
loopback mode
—
24
DIAG Decode
w1c w1c w1c w1c w1c w1c w1c w1c
23
Table 19-14. SError Field Descriptions
S
22
H
21
C
20
D
DIAG Decode
19
B
All zeros
W
18
Description
Description
IN
17
16
N
15
—
12
w1c
11
E
—
10
ERR Decode
w1c w1c
C
9
Freescale Semiconductor
T
8
7
—
Access: w1c
2
w1c w1c
M ITG
1
0