MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 982

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.7.1.8
SGMII mode initialization sequence is very similar to TBI mode initialization. Additional initialization is
required for the SerDes. An example of SGMII mode initialization sequence is shown in
14-234
Initialize SerDes to select SGMII. The initialization sequence should be prepended with SerDes initialization.
SGMII Interface Support
SGMII mode utilizes the internal TBI PHY. The internal TBI PHY only
auto-negotiates at 1 Gbps. However, 10 Mbps and 100 Mbps speeds are
supported in SGMII mode. It is recommended that the external PHY inform
the MAC if the desired link speed is not 1 Gbps. Software can perform MII
management cycles to determine the external PHY link speed and program
ECNTRL and MACCFG2 accordingly.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
RX n /RX n
TX n /TX n
Signals
Table 14-191. SGMII Interface Signal Configuration (4-Wire)
Frequency [MHz] 1250
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
Sum
Table 14-192. SGMII Mode Register Initialization Steps
(This example has Statistics Enable = 1, TBIM = 1, SGMIIM = 1)
Voltage [V] LVDS
SerDes Signals
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
ECNTRL[0000_0000_0000_0000_0001_0000_0010_0010]
(Set I/F mode = 1 in SGMII 10/100 Mbps speed)
(Set R100M = 1 in SGMII 100 Mbps speed)
I/O
O
I
to 02608C:876543, for example.
to 02608C:876543, for example.
(I/F Mode = 2, Full Duplex = 1)
Initialize MAC Station Address
Initialize MAC Station Address
Initialize MACCFG2,
Signals
No. of
Initialize ECNTRL,
Clear Soft_Reset,
Set Soft_Reset,
2
2
4
NOTE
Signals
RXD
TXD
Frequency [MHz] 1250
Sum
Voltage [V] LVDS
SGMII Interface
I/O
O
I
Signals
No. of
Freescale Semiconductor
2
2
4
Table
14-192.