MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1111

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.3.2
The PCI Express PME and message disable register, shown in
detection of the corresponding bits in the PCI Express PME and message detect register.
Offset 0x024
The fields of the PCI Express PME and message disable register are described in
Freescale Semiconductor
Reset
Reset
0–15
Bits
Bits
30
31
16
17
18
19
20
W
W
R
R PTO
16
D
0
ENL23D Entered_L2/L3 ready disable. When set, this bit disables the setting of PEX_PME_MES_DR[ENL23] bit.
EXL23D Exited_L2/L3 ready disable. When set, this bit disables the setting of PEX_PME_MES_DR[EXL23] bit.
Name
PIOF
ABP
Name
PTOD
Figure 17-8. PCI Express PME and Message Disable Register (PEX_PME_MES_DISR)
—
—
—
17
—
PCI Express PME and Message Disable Register
(PEX_PME_MES_DISR)
Power indicator off. This bit indicates the detection of an Power_Indicator_Off message. This bit is only valid
in EP mode.
1 Power indicator off message is detected
0 No power indicator off message detected
Attention button pressed. This bit indicates the detection of an Attention_Button_Pressed message. This bit
is only valid in RC mode.
1 Attention button press message is detected
0 No attention button press message detected
ENL23
Reserved
PME turn off disable. When set, this bit disables the setting of PEX_PME_MES_DR[PTO] bit.
1 Disable PME_Turn_Off_message detection
0 Enable PME_Turn_Off message detection
Reserved
1 Disable Entered_L2/L3 ready state detection
0 Enable Entered_L2/L3 ready state detection
1 Disable Exited_L2/L3 ready state detection
0 Enable Exited_L2/L3 ready state detection
Reserved
18
D
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-9. PEX_PME_MES_DR Field Descriptions (continued)
EXL23
19
D
Table 17-10. PEX_PME_MES_DISR Field Descriptions
—
20
HRD
21
D
LDDD
22
23
All zeros
All zeros
—
—
Description
Description
24
AION
25
D
Figure
AIBD AIOFD PIOND
26
17-8, when set, prevents the
27
PCI Express Interface Controller
28
Table
PIBD PIOFD ABPD
17-10.
29
Access: Read/Write
30
17-15
15
31