MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1514

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23.4.1.13 Power Management Reset Counters Configuration Register (PMRCCR)
The power management reset counter configuration register (PMRCCR), shown in
bits that configure the reset counter used in deep sleep mode.
23-22
Offset 0x084
Reset
Reset
15–24
Bits
25
26
27
28
29
30
31
W
W
R
R
16
0
0
0
DPSLPING
JOGGING
NAPPING
Figure 23-13. Power Management Reset Counters Configuration Register (PMRCCR)
DOZING
SLPING
Name
—
—
—
—
—
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
18
0
0
2
Reserved
Deep sleep status
0 Device is not attempting to reach deep sleep mode.
1 The device is attempting to DEEP SLEEP because POWMGTCSR[DPSLP] is set. Most functional
Jog status
0 No Jog request
1 Device is in jog mode. Functional blocks in the core and device are shut down or are attempting to
Reserved
Doze status
0 Device is not in doze mode.
1 The MPC8536E is in doze mode because POWMGTCSR[DOZ] is set or because HID0[DOZE] and
Nap status
0 Device is not in nap mode.
1 The MPC8536E is in nap mode because HID0[NAP] and MSR[WE] are set. The core has halted
Sleep status
0 Device is not attempting to reach sleep mode.
1 The device is attempting to SLEEP because POWMGTCSR[SLP] is set or because HID0[SLEEP]
Reserved
blocks in the core and device are shut down or are attempting to shut down.
shut down.
MSR[WE] (in the e500 core) are set. The core has halted instruction fetching, but all other
functional blocks in the core and device are running.
instruction fetching, snooping of the L1 caches is disabled, and all of the core functional units
except the timer facilities are shut down. All functional blocks in the device are running.
and MSR[WE] (in the e500 core) are set. Most functional blocks in the core and device are shut
down or are attempting to shut down.
Table 23-15. POWMGTCSR Field Descriptions (continued)
19
0
0
3
1
1
VRCNT_PRE
RCNT_PRE
1
0
0
0
23
7
0
1
Description
24
1
1
8
0
1
0
0
0
1
VRCNT
RCNT
Figure
0
0
Freescale Semiconductor
Access: Read/Write
0
0
23-13, contains
1
0
15
31
1
1