MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1565

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 24-7
PMC1–PMC9, shown in
the 64 reference events that can be counted on all of these registers.
Table 24-8
24.4
This section describes the use of some features of the performance monitor.
24.4.1
PMCs can generate an interrupt on an overflow when the msb of a counter changes from 0 to 1. For the
interrupt to be signalled, the condition enable bit (PMLCAn[CE]) and performance monitor interrupt
enable bit (PMGC0[PMIE]) must be set. When an interrupt is signalled and the
freeze-counters-on-enabled-condition-or-event bit (PMGC0[FCECE]) is set, PMGC0[FAC] is set by
hardware and all of the registers are frozen. Software can clear the interrupt condition by resetting the
performance monitor and clearing the most significant bit of the counter that generated the overflow.
Freescale Semiconductor
.
Offset 0xE_1028
Reset
0–31
Bits
0–63
W
Bits
R
0xE_1038
0xE_1048
0xE_1058
0xE_1068
0xE_1078
0xE_1088
0xE_1098
0xE_10A8
0xE_10B8
0xE_10C8
0
Functional Description
describes PMC0 fields.
describes PMCn fields.
Performance Monitor Interrupt
Name
PMC n
Name
PMC0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 24-8. Performance Monitor Counter Register (PMC1–PMC9)
Figure
Event count. An overflow is indicated when the msb = 1. Manually setting the msb can
cause an immediate interrupt.
Event count. Counts only clock cycles
24-8, are 32-bit counters that can monitor 64 unique events in addition to
Table 24-8. PMC[1–9] Field Descriptions
Table 24-7. PMC0 Field Descriptions
All zeros
PMC n
Description
Description
Device Performance Monitor
Access: Read/Write
24-11
31