MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 995

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3.1.1
The mode register allows software to start a DMA transfer and to control various DMA transfer
characteristics.
Table 15-5
Freescale Semiconductor
Offset 0x100
Reset
Reset
11–12
Bits
0–3
4–7
8–9
10
13
W
W
R
R
0x180
0x200
0x280
SAHTS DAHE SAHE
16
0
EMP_EN External master pause enable. Valid only if MR n [EMS_EN] is set.
EMS_EN External master start enable. This bit does not apply to single-write start modes (direct or chaining).
Name
BWC
17
—
—
—
describes the MRn fields.
Mode Registers (MR n )
—
18
Figure 15-4
Reserved
Bandwidth/pause control. Defined when single and multiple channels are executing or if MR n [EMP_EN] is
set in external transfer mode.
The value of MR n [BWC] determines how many bytes a given channel is allowed to transfer before the DMA
engine pauses the current channel and re-arbitrates (switches to the next channel).
In external pause mode, the value of MR n [BWC] dictates how many bytes are allowed to transfer before
pausing the channel, after which a new assertion of DREQ resumes channel operation.
0000 1 byte
0001 2 bytes
0010 4 bytes
0011 8 bytes
0100 16 bytes
0101 32 bytes
0110 64 bytes
Reserved
0 Disable the external master pause feature.
1 Enable the external master pause feature. Channel is paused as described by MR n [BWC].
Reserved
0 Disable the channel from being started by an external DMA start pin.
1 Enable the channel to be started by an external DMA start pin, which sets MR n [CS].
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
19
3
—
20
4
describes the MRn.
SRW EOSIE EOLNIE EOLSIE EIE
21
Figure 15-4. DMA Mode Registers (MR n )
BWC
Table 15-5. MR n Field Descriptions
22
23
7
All zeros
All zeros
24
8
—
Description
25
9
0111 128 bytes
1000 256 bytes
1001 512 bytes
1010 1024 bytes
1011–1110 Reserved
1111 Disable bandwidth sharing to allow
EMP_EN
XFE
10
26
uninterrupted transfers from each channel.
CDSM/SWSM
11
27
—
CA
12
28
Access: Read/Write
EMS_EN DAHTS
CTM
13
29
DMA Controller
CC CS
14
30
15-9
15
31