MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 905

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

No Ethernet-specific features (such as MAC address matching) or layer 2 properties (such as Ethertype)
are available in FIFO mode.
14.6.2.1
In the encoded (non GMII-style) FIFO modes, link-level flow control is provided to the eTSEC transmitter
on the COL signal of the controlling eTSEC, while back pressure to the remote transmitter is sent on the
CRS signal (which acts as an output signal only in FIFO mode). Owing to the synchronization delay of
responding to flow control on signal COL, the eTSEC cannot stop transmission immediately, but may
require up to 8 clock cycles before transmission is paused. The eTSEC issues flow control either when
software forces it (through the FIFOCFG[FFC] bit), or when the Rx FIFO reaches its high watermark.
14.6.2.2
If FIFOCFG[CRCAPP] is enabled, the FIFO interface automatically appends a 4-byte CRC to each
transmitted packet. Alternatively, if FIFOCFG[CRCAPP] is cleared, TxBD[TC] provides a per-packet
override to append CRC. The IEEE 802.3 standard CRC-32 algorithm is used, where the least significant
bit of each byte (TXD[0]) is combined into the CRC ahead of the most significant bit (TXD[]).
Accordingly, the CRC result, CRC[31:0] is transmitted onto the interface in bit-reversed order,
CRC[24:31], CRC[16:23], CRC[8:15], CRC[0:7].
Automatic checking of CRC-32 checksums received over the FIFO interface is enabled by setting
FIFOCFG[CRCCHK]. CRC errors are recorded in the RxBD[CR] flag of every last buffer. Like transmit,
the receiver combines data into the CRC in the order least significant data bit (RXD[0]) to most significant
bit (RXD[]). The last 4 bytes of the packet are assumed to be CRC whenever FIFOCFG[CRCCHK] is
enabled, and these bytes are returned as part of the data buffer.
Freescale Semiconductor
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If RCTRL[PRSFM]=0, received packets must be a minimum of 10 bytes.
If RCTRL[PRSFM]=1, received packets must be a minimum of 14 bytes.
Transmitted packets with L2 headers must be a minimum of 14 bytes.
Transmitted packets without L2 headers must be a minimum of 10 bytes.
Although TCP/IP offload is supported, the receive queue filer table must be limited to as many
entries as eTSEC can search every packet. See
for guidance on how to determine maximum table size for an application.
eTSEC requires received packets to have a minimum inter-packet gap of three cycles.
On transmission, the minimum inter-packet gap (set in FIFOCFG[IPG]) is three cycles if CRC is
not automatically appended. Each CRC data beat adds to this requirement. For 8-bit FIFO
interfaces the minimum is 7 cycles.
Flow Control
CRC Appending and Checking
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 14.6.5.2.1, “Filing Rules,” on page 14-184
Enhanced Three-Speed Ethernet Controllers
14-157