MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 925

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UDP). TOE provides protocol header recognition, header verification (IPv4 header checksum
verification), and TCP/UDP payload checksum verification including verification of associated
pseudo-header checksums. For large frames off-load of checksum verification saves a significant fraction
of the CPU cycles that would otherwise be spent by the TCP/IP stack. IP packet fragmentation and
re-assembly, and TCP stream establishment and tear-down are not performed in hardware. The frame
parser sets RQFPR[IPF] status flag encountering a fragmented frame. The frame parser in eTSEC searches
a maximum of 512 bytes from the start of a received frame when attempting to locate headers; headers
deeper than 512 bytes are assumed not to exist, and any associated receive status flags in the frame control
block remain cleared.
On transmit, TOE provides IPv4 and TCP/UDP header checksum generation. Like receive TOE,
checksum generation reduces CPU load significantly for TCP/IP stacks modified to exploit eTSEC TOE
functions. The eTSEC does not checksum transmitted packets with IPv6 routing headers or calculate
TCP/UDP checksums from IP fragments. If a transmitted TCP segment requires checksum generation but
IPv6 extension headers would prevent eTSEC from calculating the pseudo-header checksum, software can
calculate just the pseudo-header checksum in advance and supply it to the eTSEC as part of per-frame TOE
configuration.
14.6.4.1
Frame control blocks (FCBs) are 8-byte blocks of TOE control and/or status data that are passed between
software (driver and TCP/IP stack) and each eTSEC. A FCB always precedes the frame it applies to, and
is present only when TOE functions are being used. As
points to the initial data buffer and the FCB. The initial data buffer must be at least 8 bytes long to contain
the FCB without breaking it. Custom or received Ethernet preamble sequences also follow the FCB if
preambles are visible.
For TxBD rings, FCBs are assumed present when the TxBD[TOE/UN] bit is set by user software. The
eTSEC ignores the TxBD[TOE/UN] bit in all BDs other than those pointing to initial data buffers,
therefore FCBs must not be inserted in second and subsequent data buffers. Since TxBD[TOE/UN] can be
set under software discretion, TOE acceleration for transmit may be applied on a frame-by-frame basis.
Freescale Semiconductor
Frame Control Blocks
BD
Figure 14-145. Location of Frame Control Blocks for TOE Parameters
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
FCB
L3OS
L2 HDR
(last)
BD
L4OS
L3 HDR
Frame data, first buffer
(first)
BD
L4 HDR
(last)
BD
Figure 14-145
BD
Frame data, second buffer
Enhanced Three-Speed Ethernet Controllers
BD ring
shows, the first BD of each frame
14-177