MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 927

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6.4.3
Upon receive, the Rx FCB returns the status of frame parse and TOE functions applied to the
accompanying frame.
Freescale Semiconductor
Bytes
0–1
2–3
4–5
6–7
Offset + 0
Offset + 2
Offset + 4
Offset + 6
8–14
8–15
0–15
0–15
Bits
0–7
15
5
6
7
Receive Path Off-Load
VLN
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
VLCTL/
PTP_ID
Name
PHCS
L4OS
L3OS
CTU
NPH
PTP
CIP
Table 14-158. Tx Frame Control Block Description (continued)
—
IP
Figure 14-147
1
IP6
2
Checksum IP header enable.
0 Do not generate an IP header checksum.
1 Generate an IPv4 header checksum.
Checksum TCP or UDP header enable.
0 Do not generate a TCP or UDP header checksum. RFC 768 advises that UDP packets
1 Generate a TCP header checksum if IP = 1 and TUP = 1 and UDP = 0.
Disable calculation of TCP or UDP pseudo-header checksum. This bit should be set if IP
options need to be consulted in forming the pseudo-header checksum, as eTSEC does not
examine IP options or extension headers for TCP/IP offload on transmit.
0 Calculate TCP or UDP pseudo-header checksum as normal, assuming that the IP header
1 Do not calculate a TCP or UDP pseudo-header checksum, but instead use the value in
Reserved
Indication to the transmitter that this is a PTP packet. Enabling PTP disables per packet
VLAN tag insertion. Instead, VLAN tag will be read from the DFVLAN when the PTP field is
true.
0 Do not attempt to capture transmission event time
1 Valid PTP_ID field. When this packet is transmitted, capture the time of transmission.
Must be clear if TMR_CTRL[TE] is clear.
Layer 4 header offset from start of layer 3 header. The layer 4 header starts L4OS octets
after the layer 3 header if it is present. The maximum layer 3 header length supported is thus
255 bytes, which may prevent TCP/IP offload on particularly large IPv6 headers.
Layer 3 header offset from start of frame not including the 8 bytes for this FCB. The layer 3
header starts L3OS octets from the start of the frame including any custom preamble header
that may be present. The maximum layer 2 header length supported is thus 255 bytes.
Pseudo-header checksum (16-bit one’s complement sum with carry wraparound, but without
result inversion) for TCP or UDP packets, calculated by software. Valid only if NPH = 1.
VLAN control word for insertion in the transmitted VLAN tag. Valid only if VLN = 1.Tx PTP
packet identification number. This number will be copied into the Tx PTP packet time stamp
identification field. PTP field takes precedence over VLN field.
Figure 14-147. Receive Frame Control Block
not requiring checksum validation should have their checksum field set to zero.
has no options.
field PHCS when determining the overall TCP or UDP checksum.
TUP CIP CTU EIP
3
describes the definition for the Rx FCB.
4
RQ
5
6
ETU
7
VLCTL
8
Description
9
—
Enhanced Three-Speed Ethernet Controllers
10
11
PRO
12
PERR
13
—
14
GPFP
15
14-179