MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 355

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-63
Note that in the absence of refresh support, system software must preserve DDR SDRAM data (such as by
copying the data to disk) before entering the power-saving mode.
The dynamic power-saving mode uses the CKE DDR SDRAM pin to dynamically power down when there
is no system memory activity. The CKE pin is negated when both of the following conditions are met:
CKE is reasserted when a new access or refresh is scheduled or the dynamic power mode is disabled. This
mode is controlled with DDR_SDRAM_CFG[DYN_PWR_MGMT].
Dynamic power management mode offers tight control of the memory system’s power consumption by
trading power for performance through the use of CKE. Powering up the DDR SDRAM when a new
memory reference is scheduled causes an access latency penalty, depending on whether active or precharge
powerdown is used, along with the settings of TIMING_CFG_0[ACT_PD_EXIT] and
TIMING_CFG_0[PRE_PD_EXIT]. A penalty of 1 cycle is shown in
Freescale Semiconductor
•
•
No memory refreshes are scheduled
No memory accesses are scheduled
summarizes the refresh types available in each power-saving mode.
Table 8-63. DDR SDRAM Power-Saving Modes Refresh Configuration
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Mem Bus Clock
COMMAND
CKE
Figure 8-57. DDR SDRAM Power-Down Mode
Power Saving Mode
Sleep
NOP
Refresh Type
None
Self
SREN
—
Figure
1
NOP
8-57.
ACT
DDR Memory Controller
8-81