MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 175

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.1.1.2
Figure 4-1
Table 4-5
4.3.1.2
An alternate configuration space can be accessed by configuring the ALTCBAR and ALTCAR registers.
These are intended to be used with the boot sequencer to allow the boot sequencer to access an alternate
1-Mbyte region of configuration space. By loading the proper boot sequencer command in the serial ROM,
the base address in the ALTCBAR can be combined with the 20 bits of address offset supplied from the
serial ROM to generate a 36-bit address that is mapped to the target specified in ALTCAR. Thus, by
configuring these registers, the boot sequencer has access to the entire memory map, one 1-Mbyte block
at a time. See
Freescale Semiconductor
24–31
8–23
Bits
0–7
Offset 0x0_0000
Reset 0 0
W
R
Figure 4-1. Configuration, Control, and Status Registers Base Address Register (CCSRBAR)
0
defines the bit fields of CCSRBAR.
BASE_ADDR Identifies the16 most-significant address bits of the 36-bit window used for configuration accesses.
shows the fields of CCSRBAR.
– Perform a load of an address that does not access configuration space or the on-chip SRAM,
– Read the contents of CCSRBAR from its new location, followed by another isync.
Name
Accessing Alternate Configuration Space
Section 11.4.5, “Boot Sequencer Mode,”
but has an address mapping already in effect (for example, boot ROM). Follow this load
with an isync.
—
—
Configuration, Control, and Status Registers Base Address
Register (CCSRBAR)
The enable bit in the ALTCAR register should be cleared either by the boot
sequencer or by the boot code that executes after the boot sequencer has
completed its configuration operations. This prevents problems with
incorrect mappings if subsequent configuration of the local access windows
uses a different target mapping for the address specified in ALTCBAR.
0
0 0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Write reserved, read = 0.
The base address is aligned on a 1-Mbyte boundary.
Write reserved, read = 0
0
0 0 0 0 0 0 1 1 1 1 1
7
8
Table 4-5. CCSRBAR Bit Settings
NOTE
BASE_ADDR
for more information.
Description
1
1 1 0 1 1 1 0 0 0 0 0 0 0 0
Reset, Clocking, and Initialization
23 24
Access: Read/Write
—
4-5
31