MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1270

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
19.5.1.8
Using the CONT primitive, the link layer is capable of replacing repetitive primitive streams with
scrambled data. This reduces EMI emissions because primitives are not scrambled.
The link layer can transmit a CONT primitive at a point where it knows it must transmit a number of
repeating primitives. After a CONT primitive has been transmitted, the link layer then transmits scrambled
junk data to the PHY layer. The content of this junk data is disregarded. At the far end link layer, the
reception of a CONT primitive will cause the last received valid primitive to be implied to be repeated until
it receives the next valid non-ALIGN primitive. Transmission of a new valid primitive halts the current
CONT processing; reception of a new valid non-ALIGN primitive halts the current CONT processing.
This action can occur on transmit and receive. The link layer supports both the transmission and reception
of CONT primitives.
19.5.1.9
The link layer is responsible for ALIGN insertion and removal at a fixed frequency. A pair of ALIGN
primitives are inserted into the transmit data stream every 254 words. At the receive end, the ALIGN
primitives are stripped from the incoming data stream in the link layer.
For diagnostic purposes, the rate of ALIGNs can be increased as much as two ALIGNS per one word; for
example, ALIGN, ALIGN, data, ALIGN, ALIGN. In addition, the SEND_4_ALIGNS bit can be set to
instruct the link layer to send four ALIGNs at a time instead of two.
19.5.1.10 Debug Functionality
There are a number of useful features designed into the link layer to aid debug, as follows:
19-40
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The align insertion rate can be increased using the ALIGN_RATE register field in the command
layer.
Four error counters can be monitored by issuing register reads to the command layer: the disparity
error counter, the code error counter, the PHY internal error counter, and the control character error
counter.
A number of configuration bits in the command layer can be used to override normal primitive
insertion. For example,
— Set PRIM_OVR_STATE = (L_SendHold state (16))
— Set PRIM = 0xb5b5957c, that is, a SYNC primitive
— During the transfer, set PRIM_OVRD_EN = 1
When the link layer detects a rising edge on PRIM_OVRD_EN, it will insert one SYNC primitive
into the datastream in place of the HOLD, when the LINK_STATE reaches the L_SendHold state.
Only one HOLD primitive will be overridden; the PRIM_OVRD_EN must be cleared and written
to again to force another override to occur.
CONT Primitive Processing
ALIGN Insertion
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor