MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1380

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.5.3.3
DWords 9–15 of an isochronous transaction descriptor are nominally page pointers (4K aligned) to the data
buffer for this transfer descriptor. This data structure requires the associated data buffer to be contiguous
(relative to virtual memory), but allows the physical memory pages to be non-contiguous. Seven page
pointers are provided to support the expression of eight isochronous transfers. The seven pointers allow
for 3 (transactions) 1024 (maximum packet size) 8 (transaction records) = 24576 bytes to be moved
with this data structure, regardless of the alignment offset of the first page.
Since each pointer is a 4K-aligned page pointer, the least-significant 12 bits in several of the page pointers
are used for other purposes.
21-46
31–28
27–16
14–12
31–12
11–0
11–8
Bits
Bits
15
Buffer Pointer (Page 0) A 4K-aligned pointer to physical memory. Corresponds to memory address bits 31–12.
Transaction n
Transaction n
Length
Name
Status
Offset
PG
ioc
iTD Buffer Page Pointer List (Plus)
Name
EndPt
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Records the status of the transaction executed by the host controller for this slot. This field is a bit
vector with the following encoding:
31 Active. Set by software to enable the execution of an isochronous transaction by the host
30 Data buffer error. Set by the host controller during status update to indicate that the host controller
29 Babble detected. Set by the host controller during status update when” babble” is detected during
28 Transaction error (XactErr). Set by the host controller during status update in the case where the
For an OUT, this field is the number of data bytes the host controller will send during the transaction.
The host controller is not required to update this field to reflect the actual number of bytes transferred
during the transfer. For an IN, the initial value of the endpoint to deliver. During the status update, the
host controller writes back the field is the number of bytes the host expects the number of bytes
successfully received. The value in this register is the actual byte count (for example, 0 zero length
data, 1 one byte, 2 two bytes, etc.). The maximum value this field may contain is 0xC00 (3072).
Interrupt on complete. If this bit is set, it specifies that when this transaction completes, the host
controller should issue an interrupt at the next interrupt threshold.
These bits are set by software to indicate which of the buffer page pointers the offset field in this slot
should be concatenated to produce the starting memory address for this transaction. The valid range
of values for this field is 0 to 6.
This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. This field is
concatenated onto the buffer page pointer indicated in the adjacent PG field to produce the starting
buffer address for this transaction.
controller. When the transaction associated with this descriptor is completed, the host controller
clears this bit indicating that a transaction for this element should not be executed when it is next
encountered in the schedule.
is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast
enough during transmission (underrun). If an overrun condition occurs, no action is necessary.
the transaction generated by this descriptor.
host did not receive a valid response from the device (Time-out, CRC, Bad PID, etc.). This bit may
only be set for isochronous IN transactions.
Table 21-39. iTD Transaction Status and Control
Selects the particular endpoint number on the device serving as the data source or sink.
Table 21-40. Buffer Pointer Page 0 (Plus)
Description
Description
Freescale Semiconductor