MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 266

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

e500 Coherency Module
Table 7-2
7.2.1.2
The ECM CCB port configuration register (EEBPCR) is shown in
Table 7-3
7-4
Offset 0x0_1010
Reset 0 0 0 0 0 0 0
8–28
Bits
0–6
30–31
0–27
7
Bits
W
R
28
29
0
CORE_STRM_DIS With A_STRM_DIS, controls whether the e500 core can stream commands onto the CCB.
describes the EEBACR fields.
describes EEBPCR fields.
A_STRM_CNT
CPU_EN
A_STRM_DIS
Name
—
—
—
ECM CCB Port Configuration Register (EEBPCR)
Name
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
6
CPU_EN
Figure 7-3. ECM CCB Port Configuration Register (EEBPCR)
Reserved
CPU port enable. Controls boot holdoff mode when the device is an agent of an external host.
Specifies whether the e500 core (CPU) port is enabled to run transactions on the CCB. The CPU
boot configuration power-on reset pin (cfg_cpu_boot) determines the initial value of this bit. If the
pin is sampled as a logic 1 at the negation of reset, the CPU is enabled to boot at the end of the
POR sequence. Otherwise, the CPU cannot fetch its boot vector until an external host sets the
CPU_EN bit.
0 Boot holdoff mode. CPU arbitration is disabled on the CCB and no bus grants are issued.
1 CPU is enabled and receives bus grants in response to bus requests for the boot vector.
After this bit is set, it should not be cleared by software. It is not intended to dynamically enable
and disable CPU operation. It is only intended to end boot holdoff mode. See
“CPU Boot
Reserved
n
7
Reserved
Controls whether the ECM allows any streaming to occur.
0 Streaming is enabled.
1 Streaming is disabled.
A_STRM_DIS and CORE_STRM_DIS must both be cleared for the e500 core to be enabled
to stream address tenures that it masters.
0 Stream address tenures initiated by the e500 core, provided A_STRM_DIS is cleared.
1 Streaming of address tenures initiated by the e500 core not allowed.
Stream count. Specifies the maximum number of transactions that any master can stream
(issue sequentially without preemption) on the CCB following an initial transaction.
00 Reserved
01 One transaction can be streamed with the initial transaction.
10 Two transactions can be streamed with the initial transaction.
11 Three transactions can be streamed with the initial transaction. Default.
8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Configuration,” for more information.
Table 7-2. EEBACR Field Descriptions
Table 7-3. EEBPCR Field Descriptions
—
Description
Description
Figure
7-3.
28
CPU_RD_HI_DIS CPU_PRI
Freescale Semiconductor
29
0
Access: Read/Write
Section 4.4.3.10,
30
0
31
0