MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 191

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4.3.16
The eTSEC1 protocol inputs, shown in
the eTSEC1 controller. Note that the value latched on these signals during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in
Status Register (PORDEVSR).”
4.4.3.17
The eTSEC3 protocol inputs, shown in
the eTSEC3 controller. Note that the value latched on these signals during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in
Status Register (PORDEVSR).”
Freescale Semiconductor
TSEC1_TXD[0:1]
Functional Signal
TSEC3_TXD[0:1]
Default (11)
Functional
Default (11)
Signal
eTSEC1 Protocol
eTSEC3 Protocol
Reset Configuration
cfg_tsec1_prtcl[0:1]
Reset Configuration
cfg_tsec3_prtcl[0:1]
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
Name
Table 4-24. eTSEC1 Protocol Configuration
Table 4-25. eTSEC3 Protocol Configuration
(Binary)
Value
(Binary)
00
01
10
11
Value
00
01
10
11
Table
Table
The eTSEC1 controller operates using 8-bit FIFO protocol.
The eTSEC1 controller operates using the MII protocol (or RMII if
configured in reduced mode as described in
width”).
The eTSEC1 controller operates using the GMII protocol (or RGMII if
configured in reduced mode as described in
width”).
The eTSEC1 controller operates using the TBI protocol (or RTBI if
configured in reduced mode as described in
width”) (default).
The eTSEC3 controller operates using 8-bit FIFO protocol.
The eTSEC3 controller operates using the MII protocol (or RMII if
configured in reduced mode as described in
Width”)
The eTSEC3 controller operates using the GMII protocol (or RGMII if
configured in reduced mode as described in
Width”).
The eTSEC3 controller operates using the TBI protocol (or RTBI if
configured in reduced mode as described in
Width”) (default).
4-24, select the protocol (FIFO, MII, GMII or TBI) used by
4-25, select the protocol (FIFO, MII, GMII or TBI) used by
Meaning
Meaning
Section 23.4.1.4, “POR Device
Section 23.4.1.4, “POR Device
Reset, Clocking, and Initialization
Section 4.4.3.14, “eTSEC1
Section 4.4.3.14, “eTSEC1
Section 4.4.3.14, “eTSEC1
Section 4.4.3.15, “eTSEC3
Section 4.4.3.15, “eTSEC3
Section 4.4.3.15, “eTSEC3
4-21