MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 937

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6.5.3
Each eTSEC can maintain multiple TxBD rings (or transmission queues) to satisfy QoS requirements. The
ability to choose from a number of transmission streams dynamically is especially important during
periods of network congestion. Certain application such as voice and video streaming are delay sensitive,
but loss insensitive. For instance, VoIP applications require little bandwidth, but are highly sensitive to
latency. Conversely, FTP or SMTP protocols are delay insensitive, but loss sensitive.
eTSEC has a transmission scheduler that implements a programmable QoS regime. The scheduler is
responsible for choosing which of the prefetched TxBDs shall be processed next, and accordingly issuing
DMA requests to service the data stream described by the chosen BD(s). The scheduler cycle is one of:
If TCTRL[TXSCHED] is set to 00, no transmission scheduling occurs, and only TxBD ring 0 is polled for
new data to transmit, with DMACTRL controlling waiting or polling. TCTRL[TXSCHED], if not zero,
can be programmed to invoke one of two scheduling algorithms, namely priority-based queuing (PBQ),
and modified weighted round-robin queuing (MWRR). In all cases where TCTRL[TXSCHED] is not zero,
the scheduler can choose from among 1 to 8 TxBD rings per eTSEC, with individual rings being enabled
by the setting of TQUEUE[EN0–EN7] bits. For example, TxBD rings 3, 4, and 7 may be enabled for
scheduling by setting EN3, EN4, and EN7, and clearing all other EN bits.
Freescale Semiconductor
Table
Entry
10
11
12
1. decide on a TxBD queue,
2. transmit exactly one frame from that queue, and
3. return to deciding on another queue, in step 1.
0
1
2
3
4
5
6
7
8
9
CLE REJ AND
1
0
0
0
0
0
1
1
0
0
0
1
0
Transmission Scheduling
0
0
0
0
0
0
0
0
0
0
0
0
0
RQCTRL Fields
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
1
1
0
0
0
0
0
1
0
0
0
0
0
Table 14-165. Filer Table Example—TCP and UDP Port Filing
000_000
000_000
000_010
000_011
000_000
000_000
000_001
000_000
000_101
000_111
000_110
000_100
000_000
Q
CMP
00
01
11
00
00
00
01
00
00
00
00
01
01
1011
1111
1111
1111
1111
1111
0000
1011
1111
1111
1111
0000
0000
PID
0x0000_0006 Enter cluster if layer 4 is TCP
0x0000_0014 AND rule—FTP from TCP ports 20
0x0000_0016
0x0000_0017 telnet from TCP port 23: file to ring 3
0x0000_0000 empty entry reserved for future use
0x0000_0000 empty entry reserved for future use
0x0000_0000 end cluster; default TCP: file to ring 1
0x0000_0011 Enter cluster if layer 4 is UDP
0x0000_0801 NFS from UDP port 2049
0x0000_0208 Route from UDP port 520
0x0000_0045 TFTP from UDP port 69
0x0000_0000 End cluster; default UDP: file to ring 4
0x0000_0000 By default, file to ring 0
RQPROP
and 21: file to ring 2
Comment
Enhanced Three-Speed Ethernet Controllers
0x0000_028B
0x0000_00AF
0x0000_0C0F
0x0000_086F
0x0000_000F
0x0000_000F
0x0000_0620
0x0000_028B
0x0000_140F
0x0000_000F
0x0000_180F
0x0000_1220
0x0000_0020
RQCTRL
Word
14-189