MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1457

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setup
packet. The contents of the first setup packet will require a response in accordance with USB device
framework command set.
21.8.2
From a chip or system reset, the USB controller enters the powered state. A transition from the powered
state to the attach state occurs when the run/stop bit (USBCMD[RS]) is set to a '1'. After receiving a reset
on the bus, the port will enter the defaultFS or defaultHS state in accordance with the protocol reset
described in Appendix C.2 of the USB Specification Rev. 2.0. The following state diagram depicts the state
of a USB 2.0 device.
Freescale Semiconductor
6. Configure the ENDPOINTLISTADDR pointer.
7. Enable the microprocessor interrupt associated with the USB module and optionally change setting
8. Set USBCMD[RS] to run mode.
For information on device queue heads, refer
For additional information on ENDPOINTLISTADDR, refer to the register table.
of USBCMD[ITC].
Recommended: enable all device interrupts including: USBINT, USBERRINT, Port Change
Detect, USB Reset Received, DCSuspend.
For a list of available interrupts refer to the USBINTR and the USBSTS register tables.
After the run bit is set, a device reset will occur. The DCD must monitor the reset event and set the
DEVICEADDR register, set the ENDPTCTRLx registers, and adjust the software state as
described in the Bus Reset section of the following Port State and Control section below.
Port State and Control
All device queue heads must be initialized for control endpoints before the
endpoint is enabled. Device queue heads for non-control endpoints must be
initialized before the endpoint can be used.
Endpoint 0 is designed as a control endpoint only and does not need to be
configured using ENDPTCTRL0 register.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
NOTE
toSection 21.7, “Device Data Structures.”
Universal Serial Bus Interfaces
21-123