MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 389

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.1
Although most PIC registers have one address, some are replicated for each processor core in a
multiprocessor device. For such registers, each core accesses its separate registers using the same address,
the address decoding being sensitive to the processor core ID. A copy of the per-CPU registers is available
to each processor core at the same physical address, that is, in a private access address space that acts like
an alias to a processor’s own copy of the per-CPU registers. As shown in
initiating the read/write transaction determines which processor’s per-CPU registers to access. For more
information, see
9.3.1.1
BRR1, shown in
Table 9-7
9.3.1.2
BRR2, shown in
configuration options.
Freescale Semiconductor
Offset 0x0010
Reset 0
Offset 0x0000
16–23
24–31
0–15
Bits
W
W
R
R
0
0
describes the BRR1 fields.
Name
IPMN The minor revision of the IP block.
IPMJ
IPID
0
Global Registers
Block Revision Register 1 (BRR1)
Block Revision Register 2 (BRR2)
0
Register fields designated as write-1-to-clear are cleared only by writing
ones to them. Writing zeros to them has no effect.
Section 9.3.8, “Per-CPU (Private Access)
IP block ID.
The major revision of the IP block.
Figure
Figure
0
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
9-3, provides information about the PIC IP block.
9-4, provides information about the IP block integration option and IP block
0
0
7
IPID
Figure 9-3. Block Revision Register 1 (BRR1)
Figure 9-4. Block Revision Register 2 (BRR2)
8
0
Table 9-5. BRR1 Field Descriptions
0
0
IPINTO
0
0
0
NOTE
0
15 16
15 16
0
Description
0
Registers.”
0
0
IPMJ
0
—
0
0
Programmable Interrupt Controller (PIC)
Figure
0
23 24
23 24
0
9-44, the ID of the core
0
0
0
Access: Read only
Access: Read only
IIPCFGO
IPMN
0
0
0
0
9-19
31
31
1