MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 823

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
24–25
Bits
23
26
27
28
29
30
31
Sync’d Rx EN Receive enable synchronized to the receive stream. (Read-only)
Sync’d Tx EN Transmit enable synchronized to the transmit stream. (Read-only)
Loop Back
Rx_Flow
Tx_Flow
Rx_EN
Tx_EN
Name
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Loop back. This bit is cleared by default.
0 Normal operation.
1 Loop back the MAC transmit outputs to the MAC receive inputs.
Reserved
Receive flow. This bit is cleared by default.
Must be 0 if MACCFG2[Full Duplex] = 0.
0 The receive MAC control ignores PAUSE flow control frames.
1 The receive MAC control detects and acts on PAUSE flow control frames.
Note: Should not be set when operating in Half-Duplex mode
Transmit flow. This bit is cleared by default.
Must be 0 if MACCFG2[Full Duplex] = 0.
0 The transmit MAC control may not send PAUSE flow control frames if requested by the system.
Note: 1The transmit MAC control may send PAUSE flow control frames if requested by the
0 Frame reception is not enabled.
1 Frame reception is enabled.
Receive enable. This bit is cleared by default. If set, prior to clearing this bit, set DMACTRL[GRS] then
confirm subsequent occurrence of the graceful receive stop interrupt (IEVENT[GRSC] is set).
0 The MAC may not receive frames from the PHY.
1 The MAC may receive frames from the PHY.
0 Frame transmission is not enabled.
1 Frame transmission is enabled.
Transmit enable. This bit is cleared by default. If set, prior to clearing this bit, set DMACTRL[GTS] then
confirm subsequent occurrence of the graceful receive stop interrupt (IEVENT[GTSC] is set).
0 The MAC may not transmit frames from the system.
1 The MAC may transmit frames from the system.
Table 14-43. MACCFG1 Field Descriptions (continued)
system.Should not be set when operating in Half-Duplex mode
Description
Enhanced Three-Speed Ethernet Controllers
14-75