MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1606

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
Table 25-25
25.4
The debug features on the MPC8536E use the LBC interfaces, and the DDR SDRAM interface.
25.4.1
Debug information that is common to all the interfaces is the source ID (SID). The transaction source ID
provides enough information to determine which block or port originated a transaction including the
distinction between instruction and data fetches from the processor core.
interpretation for the 5-bit SID field. Note that the table also includes ports that are only slaves, such as
local memory. These ports are always targets. As such, the value shown represents a target ID (TID) and
not a source ID. For ports that can function in both capacities, the value indicates source ID when
mastering transactions, and target ID when responding as slave. The TID field is only meaningful when
one of the following participates in the transaction:
25-24
8–31
Bits
0–4
5–7
•
•
•
The e500 coherency module (ECM) dispatch bus
The watchpoint monitor (WMCR1[IFSEL] = 000)
The trace buffer (TBCR1[IFSEL] = 000)
Name
Value
(Hex)
SEL
Functional Description
—
—
00
01
02
03
04
05
Source and Target ID
describes the TOSR fields.
PCI Express 1
PCI Express 3
Enhanced local bus controller
USB1
PCI
PCI Express 2
Reserved
Select. Selects the source for TRIG_OUT
000 READY signal. Multiplexed with TRIG_OUT. Basic device state indicator. READY asserts whenever the
001 Selects the watchpoint monitor hit indication
010 Selects the trace buffer hit indication
011 Selects the performance monitor overflow indication
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
device is not in reset or not asleep. See
about the reset sequence, and
management states.
Source (or Target) Port
Table 25-26. Source and Target ID Values
Table 25-25. TOSR Field Descriptions
Chapter 23, “Global Utilities,”
Chapter 4, “Reset, Clocking, and Initialization,”
Value
(Hex)
Description
10
11
12
13
14
15
Local processor (instruction fetch)
Local processor (data fetch)
Reserved
Reserved
USB2
DMA
Source (or Target) Port
for more information about power
Table 25-26
shows the values and
Freescale Semiconductor
for more details