MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 940

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Once the user has determined the worst case scenario for their application, they program the required free
BD threshold into the eTSEC (through RQPRM[PBTHR]). Since different BD rings may have different
sizes and expected packet arrival rates, a separate threshold is provided for each active ring. It is
recommended that a threshold of at least fourBDs is the practical minimum for gigabit ethernet links.
For the Rx descriptor controller to determine the number of free BDs remaining in the ring, it needs to
know the following:
For each active ring, the current BD pointer (RBPTRn) is maintained by the eTSEC. Software knows both
the size of the Rx ring and the location of the last freed BD. By providing the eTSEC with those values
(through RQPRM[LEN] and RFBPTR respectively) the eTSEC always know how many receive buffers
are available to be consumed by incoming data.
The number of guaranteed free BDs in the ring is then determined by:
When RFBPTRn < RBPTRn
When RFBPTRn > RBPTRn
When RBPTRn = RFBPTRn the number of free BDs in the ring is either one (since RFBPTRn points to a
free BD) or equal to the ring length. Since the BD pointed to by RBPTRn may be either in use or about to
be used, it is not considered in the free BD count. To resolve the case where the two pointers collide, the
following logic applies:
If RBASEn was updated and thus initializes both RBPTRn and RFBPTRn, the ring is deemed empty.
If RFBPTRn is updated by a software write and matches RBPTRn, the ring is deemed empty.
If HW updates RBPTRn and the result matches RFBPTRn, the ring is deemed to have one BD remaining.
Upon writing this BD back to memory (indicating the buffer is occupied) the ring is deemed to be full.
Important. There is a possibility that if software is severely backlogged in updating RFBPTRn, the
hardware could wrap around the ring entirely, consume exactly the remaining number of BDs and not halt
with a BSY error. If software then increments RFBPTRn to the next address (thereby equalling RBPTRn),
the hardware assumes the ring is now empty (when in fact there is only a single BD freed up). This results
in the hardware failing to maintain back pressure on the far end. Upon software incrementing RFBPTRn
a subsequent time, the wrap condition is successfully detected and hardware recognizes a nearly full ring
(rather than a nearly empty one). Since software can increment RFBPTRn by any amount, it is not possible
for hardware to determine in this case whether the user has cleared the entire ring or just one BD. Users
14-192
•
1. The location of the current BD being used by hardware
2. The location of the last BD that was released (freed) by software
3. The length of the Rx BD ring.
The eTSEC receives a burst of short frames with minimum inter-frame-gap (96bit times for
ethernet)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
FreeBDs
FreeBDs
=
RQPRMn LEN
=
RFBPTRn RBPTRn
–
RBPTRn
–
+
RFBPTRn
Freescale Semiconductor