MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1499

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Configuration,”
PCI/PCI Express host/agent mode (described in
For more information about the PCI configurations, see
(PBFR).” Figure 23-5
Freescale Semiconductor
10–11
Offset 0x004
Reset
Reset
Bits
1–3
4–7
8–9
12
0
W
W
R BCFG
R
ROM_LOC Location of boot ROM. This field reflects the values on cfg_rom_loc[0:3] at the negation of HRESET.
16
BSCFG
n
0
0
Name
BCFG
—
—
—
0
0
1
and
CPU boot configuration
0 The CPU is prevented from booting until configuration by an external master is complete.
1 The CPU is allowed to start fetching boot code.
Reserved
0000 PCI
0001 PCI Express 1
0010 PCI Express 2
0011 PCI Express 3
0100 DDR Controller
0101 Reserved
0110 On-chip boot ROM SPI configuration
0111 On-chip boot ROM eSDHC configuration
1000 Local bus FCM: 8-bit NAND Flash small page ECC enabled
1001 Local bus FCM: 8-bit NAND Flash small page ECC disabled
1010 Local bus FCM: 8-bit NAND Flash large page ECC enabled
1011 Local bus FCM: 8-bit NAND Flash large page ECC disabled
1100 Reserved
1101 Local bus GPCM: 8-bit ROM
1110 Local bus GPCM:16-bit ROM
1111 Local bus GPCM: 32-bit ROM (Default)
Reserved
Boot sequencer configuration
00 Reserved
01 Boot sequencer enabled with normal I
10 Boot sequencer enabled with extended I
11 Boot sequencer disabled
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 4.4.3.11, “Boot Sequencer
—
0
0
describes the bit settings of the PORBMSR.
Figure 23-2. POR Boot Mode Status Register (PORBMSR)
3
0
0
Table 23-5. PORBMSR Field Descriptions
n
0
4
ROM_LOC
n
0
n
0
Section 4.4.3.7, “Host/Agent
n
0
7
2
C addressing
2
—
C addressing
Configuration”) and the default settings of
Description
Section 16.3.2.19, “PCI Bus Function Register
8
0
0
—
0
0
9
10
n
0
BSCFG
11
n
0
Configuration”).
—
12
0
0
13
Access: Read only
n
0
Global Utilities
HA
n
0
15
31
n
0
23-7