MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1325

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.6.3.2
20.6.3.2.1
For block reads, the basic unit of a data transfer is a block whose maximum size is stored in areas defined
in corresponding card specifications. A CRC is appended to the end of each block, ensuring data transfer
integrity. CMD17, CMD18, CMD53, and so on, can initiate a block read. After completing the transfer,
the card returns to the transfer state.
For multi-block reads, data blocks are continuously transferred until a stop command is issued. If the host
uses partial blocks whose accumulated length is not block aligned and block misalignment is not allowed,
the card which does not support partial block length, should detect the block misalignment at the beginning
of the first misaligned block and report the error, depending on its card type.
For simplicity, the software flow described below incorporates the internal DMA, and the read operation
is a multi-block read with Auto CMD12 enabled. For the other method (CPU polling status) and different
transfer nature, the internal DMA part should be removed and the alternative steps are straightforward.
20.6.3.2.2
In general, the read operation is not able to pause.
Similar to the flow described in
same type of read operations:
Freescale Semiconductor
1. Check the card status and wait until the card is ready for data.
2. Set the card block length.
3. Set eSDHC BLKATTR[BLKSIZE] to the same as the block length set in the card in step 2.
4. Set eSDHC BLKATTR[BLKCNT] with the number of blocks to send.
5. Disable the buffer read ready interrupt, configure the DMA setting, and enable the eSDHC DMA
6. Wait for the transfer complete interrupt.
7. Check the status bit to see if a read CRC error or any other errors occurred between sending Auto
1. Set PROCTL[RWCTL].
2. Check the card status and wait until the card is ready for data.
3. Set the card block length.
4. Set eSDHC BLKATTR[BLKSIZE] to the same as the block length set in the card in Step 2.
5. Set eSDHC BLKATTR[BLKCNT] with the number of blocks to send.
6. Disable the buffer read ready interrupt, configure the DMA setting, and enable the eSDHC DMA
7. Set PROCTL[SABGREQ].
8. Wait for the transfer complete interrupt.
— MMC/SD cards — use SET_BLOCKLEN (CMD16)
when sending the command with data transfer. Set XFERTYP[AC12EN].
CMD12 and receiving the response.
— MMC/SD cards — use SET_BLOCKLEN (CMD16)
when sending the command with data transfer. Set XFERTYP[AC12EN].
Block Read
Normal Read
Read with Pause
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 20.6.3.2.1, “Normal Read,”
the read with pause is shown with the
Enhanced Secure Digital Host Controller
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