MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 694

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Enhanced Local Bus Controller

The banks selected to work with the GPCM support an option to drive the LCSn signal with different

timings (with respect to the external address/data bus). LCSn can be driven in any of the following ways:

Simultaneous with the latched memory address. (This refers to the externally latched address and

not the address timing on LAD. That is, the chip select does not assert during LALE).

Option Register Attributes

lists the signal timing parameters for a GPCM write access as the option register attributes are

Chip-Select Assertion Timing

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Table 13-33. GPCM Write Control Signal Timing

Signal Timing (LCLK clock cycles)

Freescale Semiconductor