MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 135

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2
Memory Map
This chapter describes the MPC8536 memory map. An overview of the local address map is followed by
a description of how local access windows are used to define the local address map. The inbound and
outbound address translation mechanisms used to map to and from external memory spaces are described
next. Finally, the configuration, control, and status registers are described, including a complete listing of
all memory-mapped registers with cross references to the sections detailing descriptions of each.
2.1
The MPC8536 provides an extremely flexible local memory map. The local memory map refers to the
36-bit address space seen by the processor as it accesses memory and I/O space. DMA engines also see
this same local memory map. All memory accessed by the DDR SDRAM and local bus memory
controllers exists in this memory map, as do all memory-mapped configuration, control, and status
registers.
The local memory map is defined by a set of 12 local access windows. Each of these windows maps a
region of memory to a particular target interface, such as the DDR SDRAM controller or the PCI
controller. Note that the local access windows do not perform any address translation. The size of each
window can be configured from 4 Kbytes to 32 Gbytes. The target interface is specified using the codes
shown in
Freescale Semiconductor
Table
Local Memory Map Overview and Example
2-1.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI
PCI Express 2
PCI Express 1
PCI Express 3
Enhanced local bus
Configuration space
DDR SDRAM
Source/Target Interface
Table 2-1. Target Interface Codes
Target Code
00000
00001
00010
00011
00100
01000
01111
2-1