MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 717

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 13-61
The following events initiate a UPM cycle:
The RAM array contains 64 words of 32-bits each. The signal timing generator loads the RAM word from
the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the UPM reads a RAM
word with WAEN set, the external LUPWAIT signal is sampled and synchronized by the memory
controller and the current request is frozen.
13.4.4.1
A special pattern location in the RAM array is associated with each of the possible UPM requests. An
internal device’s request for a memory access initiates one of the following patterns (MxMR[OP] = 00):
A UPM refresh timer request pattern initiates a refresh timer pattern (RTS).
An exception (caused by a bus monitor time-out error) occurring while another UPM pattern is running
initiates an exception condition pattern (EXS).
Freescale Semiconductor
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Any internal device requests an external memory access to an address space mapped to a
chip-select serviced by the UPM
A UPM refresh timer expires and requests a transaction, such as a DRAM refresh
A bus monitor time-out error during a normal UPM cycle redirects the UPM to execute an
exception sequence
Read single-beat pattern (RSS)
Read burst cycle pattern (RBS)
Write single-beat pattern (WSS)
Write burst cycle pattern (WBS)
LUPWAIT
UPM Requests
shows the basic operation of each UPM.
Memory Access Request
Figure 13-61. User-Programmable Machine Functional Block Diagram
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(issued in software)
Exception Request
Internal / External
Run Command
Timer Request
UPM Refresh
Request
Logic
Wait
Hold
Generator
WAEN Bit
Index
Array
(LAST = 0)
Increment
Index
Index
Internal Controls
Internal
Signals
Latch
RAM Array
Generator
Signals
Timing
Enhanced Local Bus Controller
LGPL n
LBS n
LCS n
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