MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 187

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4.3.9
The device can be configured with different I/O ports active
configuration of I/O ports and bit rates (and required reference clocks) that are possible for
interfaces.
4.4.3.10
The CPU boot configuration input, shown in
is sampled low at reset, the e500 core is prevented from fetching boot code until configuration by an
external master is complete. The external master frees the CPU to boot by setting EEBPCR[CPU_EN] in
the ECM CCB port configuration register (EEBPCR). See
Register (EEBPCR),”
Freescale Semiconductor
TSEC1_TXD2,
TSEC3_TXD2,
PULSE_OUT1
TSEC_1588_
Default (111)
Functional
Signal
SerDes2 I/O Port Selection
CPU Boot Configuration
Any disabled SATA controller(s) will have their respective bit(s) set in
DEVDISR (see
and therefore cannot respond to configuration accesses, as described in
Section 23.5.1.5, “Shutting Down Unused
Reset Configuration
cfg_srds2_prtcl[0:2]
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
for more information.
Section 23.4.1.10, “Device Disable Register
Table 4-17. SerDes2 I/O Port Selection
(Binary)
Value
000
001
010
011
100
101
110
111
Reserved
SATA1
SATA2
eTSEC1 and eTSEC3 Ethernet interface uses parallel interface according
to POR config inputs cfg_tsec1_prtcl and cfg_tsec3_prtcl.
Reserved
SATA1
SATA2 disabled.
eTSEC1 and eTSEC3 Ethernet interface uses parallel interface according
to POR config inputs cfg_tsec1_prtcl and cfg_tsec3_prtcl.
SerDes2 Lane B disabled.
SATA1 and SATA2 disabled.
eTSEC1 SGMII (1.25 Gbps)
eTSEC3 SGMII (1.25 Gbps)
POR config inputs cfg_tsec1_prtcl and cfg_tsec3_prtcl should be left in
their default settings.
Reserved
SATA1 and SATA2 disabled.
eTSEC1 SGMII (1.25 Gbps)
cfg_tsec1_prtcl should be left in its default setting)
eTSEC3 parallel mode Ethernet interface (according to cfg_tsec3_prtcl).
SerDes2 Lane B disabled
SATA1 and SATA2 disabled.
eTSEC1 and eTSEC3 Ethernet interface uses parallel interface according
to POR config inputs cfg_tsec1_prtcl and cfg_tsec3_prtcl.
SerDes2 disabled
Table
NOTE
4-18, specifies the boot configuration mode. If LA27
SerDes2 Lane A.
SerDes2 Lane B.
SerDes2 Lane A.
Section 7.2.1.2, “ECM CCB Port Configuration
Blocks.”
on SerDes2
SerDes2 Lane A.
SerDes2 Lane B.
SerDes2 Lane A (POR config input
Meaning
.
Table 4-17
(DEVDISR)”),
Reset, Clocking, and Initialization
shows the
SerDes2
4-17