MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 779

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.1.4
The interrupt mask register provides control over which possible interrupt events in the IEVENT register
are permitted to participate in generating hardware interrupts to the PIC. All implemented bits in this
register are R/W and cleared upon a hardware reset. If the corresponding bits in both the IEVENT and
IMASK registers are set, the PIC receives an interrupt (for each eTSEC these are grouped into transmit,
receive, and error/diagnostic interrupts). The interrupt signal remains asserted until either the IEVENT bit
is cleared, by writing a 1 to it, or by writing a 0 to the corresponding IMASK bit.
Freescale Semiconductor
Bits
27
28
29
30
31
Name
PERR
FGPI
DPE
FIQ
FIR
Interrupt Mask Register (IMASK)
a frame that matches a GPI rule sequence that is specified in the filer. It is synchronized with the setting of
RXF.
0 No filer generated interrupt has occurred.
1 The filer has accepted a frame via a matching rule that the RQFCR[GPI] bit set.
The receive queue filer result is invalid, either because not enough time between frames was available to
find a matching rule, or no entry in the filer table could be matched.
0 Receive queue filer reached a definite result; however, bit FIQ may still be set if a frame was filed to a
1 Receive queue filer was unable to reach a definite result. In this case, bit FIQ is also set if no entry in the
Filed frame to invalid receive queue. This bit indicates that either the receive queue filer chose to DMA a
received frame to a disabled RxBD ring, or that no rule in the filer table could be matched.
0 Received frames filed to valid queues or rejected. Note that a frame may be rejected if the filer has
1 Received frames filed to RxBD rings that are not enabled. The frame is discarded. If bit FIR is also set
which is likely to compromise the validity of recently transferred frames.
0 No parity errors detected.
1 Data held in the FIFO or filer arrays is expected to be corrupted due to a parity error.
unambiguously, due to encapsulated header type fields contradicting each other.
0 Received frame parsed successfully.
1 Received frame parse revealed header inconsistencies.
Filer generated general purpose interrupt on a set of filer rule match. This bit will be set upon reception of
Internal data parity error. This bit indicates that the eTSEC has detected a parity error on its stored data,
Receive frame parse error for TCP/IP off-load. This bit indicates that a received frame could not be parsed
disabled RxBD ring.
filer table could provide a rule match.
insufficient time to reach a conclusive result between frames, in which case bit FIR is set.
this indicates that the filer exhausted all of its table entries without a rule match.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-8. IEVENT Field Descriptions (continued)
Description
Enhanced Three-Speed Ethernet Controllers
14-31